Enabling Novel innovation in Containers profile Sculpting for Cell Structure improvement
As dynamic random-access memory (DRAM) technology continues to scale, the shrinking capacitor feature size presents a significant challenge in engineering an optimal container profile. Advanced nodes demand minimized Top Capacitor film (TCF) bowing critical dimension to mitigate risks such as cell‑to‑cell shorts and High‑K pinch‑off, while simultaneously requiring enlarged bottom capacitor film (BCF) critical dimension (CD) to enhance cell capacitance. This work demonstrates a breakthrough using a novel container pre‑deposition cleaning chemistry that mixes a dilute sulfuric peroxide mixture with low‑concentration HF (DSP+). The new formulation achieves improvement in etch selectivity between BCF and TCF without compromising post‑etch cleaning efficiency. Through systematic formulation studies and chemical time‑skew experiments, DSP+ enables reduced TCF etch loss and a more vertical container profile. These improvements translate directly into enhanced capacitance performance, offering a promising pathway for future DRAM capacitor scaling.
BIOGRAPHY
Adara Yang received her Bachelor’s degree in Science (Chemistry) from the National University of Singapore in 2006. In the same year, she joined Micron Semiconductor Asia (Singapore) as a Process Engineer in the Wet Process module, beginning a long‑standing career focused on semiconductor manufacturing and process integration.
She currently serves as a Member of Technical Staff (MTS) at Micron Singapore, supporting front‑end DRAM manufacturing with an emphasis on advanced wet clean and etch process integration. Her technical scope spans container and high‑aspect‑ratio structure cleaning, bevel and backside processes, and BEOL wet applications, where precise control of chemical interactions and profile integrity is critical to device performance and yield.
Adara works closely with cross‑functional teams across process integration, equipment engineering, and yield to translate laboratory findings into high‑volume manufacturing solutions. Her experience on single‑wafer wet clean platforms and her systematic approach to process characterization have supported both technology development and manufacturing excellence.
With nearly two decades of experience in semiconductor wet processing, Adara continues to contribute to Micron’s DRAM technology roadmap through sustained innovation, strong execution, and collaborative problem‑solving. Her professional interests include advanced wet chemistry applications, process robustness for next‑generation nodes, and scalable solutions that balance device performance, cost, reliability, and manufacturability.