Advanced Topography Correction Planarization Technology for Yield Enhancement
ABSTRACT
The evolution of advanced semiconductor processes, such as Backside Power Delivery Networks (BSPDN) and wafer bonding technologies, has introduced severe topography challenges. Consequently, stringent wafer planarity requirements now extend beyond the center to the wafer edge and the entire backside. Current topography issues, including Edge Roll-Off (ERO) caused by standard processes and unwell bonded gaps, severely impact edge yield. Furthermore, backside defects frequently lead to Extreme Ultraviolet (EUV) defocus and e-chuck damage. Conventional edge rebuilds and backside processes suffer from high manufacturing costs, profile asymmetry, and a heavy reliance on chemical consumables. To address these critical bottlenecks, we present the new technologies as a cost-effective and
efficient edge and backside planarization solution. Unlike conventional multi-step methods, the Ebara system provides precise profile control with required accuracy in devices and advanced asymmetry correction capabilities. Crucially, this is achieved without the use of
slurry, process gases, or chemicals, leading to significant reductions in water and fab-material consumption. Additionally, this technology saves on thin-film and conventional CMP costs. Ultimately, this comprehensive topography correction solution addresses the pressing yield and defect challenges in modern 3D-NAND, DRAM EUV, and logic BSPDN applications, ensuring profitability for cutting-edge semiconductor manufacturing
BIOGRAPHY
Dr. Ji Chul Yang is a distinguished semiconductor expert with 28 years of comprehensive experience in semiconductor processes for various integrated circuits, including NAND, DRAM, and Logic devices. Currently serving as the Chief of Technology Executive at EBARA, he has held senior technical and research leadership roles at industry giants including Samsung Semiconductor, GlobalFoundries, and SK Hynix. Specializing in CMP and cleaning processes, Dr. Yang possesses a deep understanding of device physics, mechanical engineering, and tribology. His career is defined by technical pathfinding, ranging from leading logic and memory cleaning and CMP projects to pioneering future semiconductor hardware and equipment sensors. A prolific researcher, he has published over 15 SCI papers and has been an invited speaker at more than 20 international conferences. He holds a Ph.D. in Semiconductor & Display Engineering and served as a Visiting Professor at Clarkson and Sungkyunkwan Universities.