J. Andres Torres holds a B.S. in Chemical Engineering from the National Autonomous University of Mexico, an M.S. in Chemical Engineering from UW-Madison, and a PhD degree in Electrical Engineering from the Oregon Health and Science University. He has been investigating the interactions between the manufacturing process and electronic design flows to exploit areas of design and process co-optimization that provide more predictable and manufacturable designs. He has been with Mentor Graphics’ Design to Silicon division since 2001 working in the areas of Resolution Enhancement Technologies, Design for Manufacturing, and Process Hardening Layout Techniques. He has published over fifty papers and holds eight patents in the area of semiconductor manufacturing and he is currently the Advanced RET Flow Architect in the Design to Silicon Division focusing in the enablement of new resolution enhancement technologies such as Directed Self Assembly, selective etch, and deposition processes, as well as applying machine learning techniques in semiconductor manufacturing processes to improve yield and productivity.