Erik Byers earned a BS in Chemical Engineering from the University of Washington in 1994. Upon graduation, he started his career at Micron as a lithography engineer in Manufacturing in Boise, Idaho. After several years in Manufacturing, he moved to R&D where he led the R&D Lithography team developing future DRAM and NAND semiconductor processes. Since then, he has served in a number of leadership roles leading both small and large teams in R&D, including an overseas assignment in Hiroshima, Japan.
Erik is currently the VP of DRAM and Next Generation Memory Process Development at Micron’s R&D site in Boise, Idaho. His team, both in the US and Japan, is developing the memory technology that will power the Cloud, Artificial Intelligence, and other future digital innovations.
Erik has been granted 15 patents, primarily in the area of semiconductor multi-patterning and imaging optimization.