DRAM

The global chip market has hit the bottom of this cycle and will rebound next year, with memory poised for growth in the second of 2023 driven by a resurgence in server investments, Soo-Kyoum Kim, Vice President of IDC, predicted in a presentation at SEMI Korea Members Day.

In the long unfolding arc of technology innovation, artificial intelligence (AI) looms immense. In its quest to mimic human behavior, the technology touches energy, agriculture, manufacturing, logistics, healthcare, construction, transportation and nearly every other imaginable industry – a defining role that promises to fast track the fourth Industrial Revolution. And if the industry oracles have it right, AI growth will be nothing shy of explosive.“The gains these days are not incremental,” said Ajit Manocha, SEMI president and CEO, said to a gathering in July of the Chinese American Semiconductor Professional Association (CASPA) for its Summer Symposium at SEMI’s headquarters in Milpitas. “They are hockey stick – exponential – with AI semiconductors growing in market size from $4 billion this year to $70 billion in 2025.”Manocha left little doubt that AI is remaking the semiconductor industry and, in the process, the world at large. Internet of Things (IoT) and 4G/5G, both key AI enablers, will account for more than 75 percent of device connections by 2025.“Today, 30 billion devices worldwide are connected,” Manocha said, citing an Applied Materials prediction that the number of connected devices globally will grow to between 500 billion and 1 trillion by 2030. Those devices will generate stunning amounts of data collected, interpreted and used to reason, solve problems, learn and plan, leading to the holy grail of autonomous machine behavior.To process this colossal amount of data central to the promise of AI, the industry must break through the limits of a key technology: memory. Memory a Critical AI BottleneckThe challenge for memory starts with performance. Historically, every decade gains in compute performance have outpaced improvements in memory speed by 100 times, and over the past 20 years that gap has grown, said Steven Woo, a fellow and distinguished inventor at Rambus, presenting at the symposium. The upshot is that memory has bottlenecked compute and, in turn, AI performance. The industry has responded with new ways to implement memory systems on AI chips. Each is suited to unique performance requirements and, of course, comes with trade-offs. Among the frontrunners: On-chip memory delivers the highest bandwidth and power efficiency but is limited in capacity. HBM (High Bandwidth Memory) offers both very high memory bandwidth and density. GDDR balances trade-offs among bandwidth, power efficiency, cost and reliability. Since 2012, AI training capability has grown 300,000 times, besting Moore’s law by 25,000 times in doubling every 3.5 months, a blistering pace compared to the 18-month doubling cycle of Moore’s law, Woo said. The staggering improvements have been driven by parallel computing capacity and new application-specific silicon like Google’s Tensor Processing Unit (TPU).These specialized silicon architectures and parallel engines are key to sustaining future gains in compute performance and combatting the slowing of Moore’s Law and the end of power scaling, Woo said. By rethinking the way processors are architected for certain markets, chipmakers can develop dedicated hardware capable of operating with 100 to 1,000 times greater energy efficiency than general purpose processors to overcome another big limiter to scaling compute performance – power.For its part, the memory industry can improve performance by signaling at higher data rates and using stacked architectures like HBM for greater power efficiency and performance, and by bringing compute closer to the data.Memory scaling for AIA key challenge is scaling memory for AI. Demand for better voice, gesture and facial recognition experiences and more immersive virtual reality and augmented reality interactions is tremendous, said Bill En, senior director at AMD, speaking at the symposium. These capabilities require more processing power across both high-performance computing (HPC) for big data analytics and machine learning as it relies on AI and machine intelligence to generate meaningful insights. Emerging machine learning applications include classification and security, medicine, advanced driver assistance, human-aided design, real-time analytics and industrial automation. And with 75 billion IoT-connected devices – all generating data – expected by 2025, there will be no shortage of data to analyze, En said. The wings alone of a new Airbus A380-1000 feature some 10,000 sensors.Mountains of this data are stored in massive data centers on magnetic hard drives, then transferred to DRAM before moving to SRAM within the CPU for the handoff to the compute hardware for analysis.With data growing at an exponential clip, the question is how to make sure all other memory systems can handle the flood of data. AMD’s answer is a chiplet architecture featuring eight smaller chips around the edge that drive the compute and a large chip in the center that doubles the IO interface and memory capability to in turn double chip bandwidth.AMD has also moved from a legacy GDDR5 memory chip configuration to HBM to bring memory bandwidth closer to the GPU for more efficient processing of AI applications. The HBM provides much higher bandwidth while reducing power consumption. Compared to DRAM, AMD’s HBM delivers a much faster data rate and far greater memory density, En said.Over the next decade, look for more performance improvements from multi-chip architectures, innovations in memory technology and integration, aggressive 3D stacking and streamlined system-level interconnects, he said. The industry will also continue to drive performance gains in devices, compute density and power through technology scaling.Michael Hall is a global marketing communications manager at SEMI.

The more than 53,000 people who flocked to SEMICON Korea last month were treated to a motherlode of insight into the future of the semiconductor industry as 470 companies exhibited innovative technologies in more than 2,000 booths. But the annual event’s most arresting numbers came in keynotes and other presentations pointing to the extraordinary industry growth that lies ahead.“It is no exaggeration to say that 90 percent of the world’s data has been generated in the last few years,” said Jim Feldhan, president of Semico Research. “This explosive growth of data is expected to continue. That's why server shipments will grow by 20.3 percent, or 30 million units, this year alone.”Feldhan said that the Internet of Things (IoT) will be a chief driver of semiconductor industry growth, with IoT expected to be applied in areas as varied as automotive, smart cities, edge computers, finance, architecture, agriculture and healthcare. For its part, artificial intelligence (AI) will start to exercise human-like judgment. Feldhan noted that in many instances in these fields, “it is more accurate to apply AI and vision systems than to rely on traditional decision-making.”Yoon Jong Lee, senior vice president of DB HiTek, predicted that the Internet, AI and 5G will drive market growth. “Looking back over the past 30 years, semiconductor market growth was powered by PCs, the Internet and cell phones, yet last year memory accounted for 35 percent of total semiconductor sales, more than double the figure in 2016,” he said. He predicted that, in 2019, the foundry sector will outstrip the semiconductor market in growth, noting that the average growth rate of the semiconductor industry is expected to be 4.1 percent, compared to 7.1 percent for the foundry market. Clark Tseng, director of SEMI, reported that the strong semiconductor growth in 2018 is unlikely to continue in 2019 due to the decline in memory pricing, as well as mobile and PC demand. “Demand for semiconductors is likely to decline in the first half as the industry is still digesting inventory and rebound in the second,” Tseng said. Semiconductor industry growth headwinds include decreases in high-end smartphone purchases, PC demand and demand for DRAMs for servers in data centers, Tseng said. Declines in economic growth and consumption in China and the U.S.-China trade war will also contribute to a slowdown. However, Tseng noted that, over the long term, technology innovation will continue and that the semiconductor industry’s prospects remain bright.One key innovation will be the elimination of AI’s reliance on Internet connections in the future. In his opening day keynote, Eunsoo Shim, senior vice president at Samsung Electronics, emphasized that AI technology that operates without the Internet in the future is essential. “We are developing 'on-device AI' technology that incorporates AI algorithms in products such as smartphones and autonomous vehicles,” he said. "When on-device AI technology is implemented, it reduces reliance on the Internet, battery consumption, and data latency.” Reducing latency will significantly improve device response time.Walden C. Rhines, CEO Emeritus of Mentor, a Siemens business, predicted that AI will fuel rapid memory growth. The memory semiconductor (DRAM, NAND flash) market is expected to see a temporary slowdown this year, with the market expected to rebound in 2020. Rhines said that memory could be seen as an early market with rapid future growth, citing memory market super-booms in 1995 and 2000.“Memory production has not decreased since 1995 or 2000,” he said. “Although memory prices will temporarily fall this year after significant market growth in 2017 to 2018, the market will continue to grow as memory production increases,” he said. Rhines added that “although memory prices will drop by about 10 percent this year, he believes prices will increase 6 percent next year.” He also predicted the steady growth of the non-memory semiconductor market as AI technology matures and China’s investment in fabless companies continues.Indeed, SEMICON Korea speakers made it clear that concerns about the growth of the semiconductor industry are expected to be short-lived. While overall growth is likely to slow in 2019, the industry is expected to rebound steadily – powered by the semiconductor industry paradigm shift led by AI, IOT, and autonomous driving – and reach a new high of nearly $541 billion in 2020.Jaegwan Shim is a marketing specialist at SEMI Korea.

Even for someone who has been in this industry since the days of the TI Datamath 4-function calculator and the TMS1100 4-bit microcontroller (yes, that’s been a LONG time – the movie Grease premiered the same year!), it is sometimes hard to grasp the scope and complexity of what happens in today’s leading-edge semiconductor gigafabs. In fact, the only way to comprehend the enormous volume of transactions that occur is to consider what happens in a single minute – this is illustrated in the infographic we have labeled “The Gigafab Minute.”* It’s amazing enough to think that a single factory can start 100,000 wafers every month on their cyclical journey through 1500 process steps… and have 99%+ of them emerge 4 months later to be delivered to packaging houses and then on to waiting customers. It’s quite another to realize that all of this happens continuously (24 x 7) and automatically. “How is this possible?” you ask.Well, a big part of the solution is the body of SEMI standards which have evolved since the early 80s to keep pace with the ever-changing demands of the industry. From an automation standpoint, many of these standards deal with the communications between manufacturing equipment and the factory information and control systems that are essential for managing these complex, hyper-competitive global enterprises.A significant characteristic of these standards is that they have been carefully designed to be “additive.” This means that new generations of SEMI’s communications standards do not supplant or obsolete the previous generations, but rather provide new capabilities in an incremental fashion. To appreciate the importance of this in actual practice, consider how the GEM, GEM300, and EDA/Interface A standards support the transactions that occur in a single Gigafab Minute.Starting at 1:00 o’clock on the infographic and moving clockwise, you first notice that 2.31 wafers enter the line. Of course, these are actually released in 25-wafer 300mm FOUPs (Front-Opening Unified Pod), but 100K wafers per month translates to 2.31 per minute. Since these factories run continuously, once the line is full, it stays full. And with an average total cycle time of 4 months, this means that there are 400K wafers of WIP (work in process) in he factory at any given time. This number, and the total number of equipment (5000+), drive the rest of the calculations.GEM (Generic Equipment Model) – SEMI E30, etc.The GEM messaging standards were initially defined in the early 90s to support the factory scheduling and dispatching applications that decide what lots should go to what equipment, the automated material handling systems that deliver and pick-up material to/from the equipment accordingly, the recipe management systems that ensure each process step is executed properly, and the MES (Manufacturing Execution System) transactions that maintain the fidelity of the factory system’s “digital twin.”Every minute of every day, GEM messages support and chronicle the following activities: 240 process steps are completed (i.e., 240 25-wafer lots are processed), 300 recipes are downloaded along with a set of run-specific adjustable control parameters, and 600 FOUPs are moved from one place to another (equipment, stockers, under-track storage, etc.). For each of these activities, the factory’s MES is notified instantaneously.GEM300 – SEMI E40, E87, E90, E94, E157With the advent of 300mm manufacturing in the mid-to-late 90s, a global team of volunteer system engineers from the leading chip makers defined the GEM300 standards to support fully automated manufacturing operations. Starting at 5:00 o’clock on the infographic, the number of transactions per minute jumps almost 3 orders of magnitude, from the monitoring of 900 control jobs across 4000 process tools to the tracking of 360,000 individual recipe step change events. This level of event granularity is essential for the latest generation of FDC (Fault Detection and Classification) applications, because precise data framing is a key prerequisite for minimizing the false alarm rate while still preventing serious process excursions. In this context, more than 6000 recipe-, product- and chamber-specific fault models may be evaluated every minute.Simultaneously, the applications that monitor instantaneous throughput to prevent “productivity excursions” and identify systemic “wait time waste” situations depend on detailed intra-tool wafer movement events. In a fab with hundreds of multi-chamber, single-wafer processes, 75,000 or more of these events occur every minute. EDA (Equipment Data Acquisition) – SEMI E120, E125, E132, E134, E164, etc.Rounding out the SEMI standards in our example gigafab is the suite of EDA standards which complement the command and control functions of GEM/GEM300 with flexible, high-performance, model-based data collection. The EDA standards enable the on-demand collection of the volume and variety of “big data” required from the equipment to support the advanced analysis, machine learning, and other AI (Artificial Intelligence) applications that are becoming increasingly prevalent in leading semiconductor manufacturers. As EUV (Extreme Ultraviolet) lithography moves from pilot production to high-volume manufacturing at the 7nm process node and beyond, the litho process area will become a major source of process data by itself, generating 10 GB of data every minute. This is in addition to the 100 GB of data collected from other process areas. The End ResultThe final wedge (12:00 o’clock) in our infographic highlights the real objective – which is producing the millions of integrated circuits that fuel our global economy and provide the technologies that are an integral part of our modern way of life. Assuming a nominal die size of 50 square mm (typical of an 8 GB DRAM), the 2.31 wafers we started at 1:00 o’clock result in almost 3200 individual chips. But none of this would be possible without the pervasive factory automation technology we now take for granted. So, as you finish reading this posting on whatever device you happen to be using, take a micro-moment to acknowledge and thank the hundreds of standards volunteers whose insights and efforts made this a reality!You may not be responsible for running a gigafab anytime soon, but the SEMI standards used in this setting are no less applicable to any Smart Manufacturing environment. Give us a call if you’d like to know more about how these technologies can benefit your operations for many years to come.Alan Weber is Vice President, New Product Innovations, at Cimetrix Incorporated. Previously he served on the Board of Directors for eight years before joining the company as a full-time employee in 2011. Alan has been a part of the semiconductor and manufacturing automation industries for over 40 years. He holds bachelor’s and master’s degrees in Electrical Engineering from Rice University. For more information on SEMI Standards, please click here.

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Diverging viewpoints on EUVL readiness for 5nmMike Lercel, Director of Strategic Marketing at ASMLASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of AmericaRenwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers' public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i's better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it's too early to say.Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It's unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIESLevinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.” Mask development for 5nmChristopher C. Progler, CTO Strategic Planning at PhotronicsProgler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.” More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.” Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; SOURCE: GLOBALFOUNDRIES Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.” How does the industry get to 3nm? ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame. Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. "We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.Debra Vogler, SEMI

The growth of China’s semiconductor industry outstripped sector expansion in many other regions in 2017 thanks in part to heavy government investments and supportive state policies. But China’s chip industry also struggled under the weight of overheated investment, inconsistent project quality, insufficient investment in research and development, a poor ability to innovate, and barriers to international cooperation. To overcome these headwinds to growth, China must identify global trends in the development of global semiconductor industry and better understand the forces it needs to mobilize to further expand its own semiconductor sector. AI and 5G fuel global semiconductor industry growthIn 2017, global semiconductor industry revenue reached a seven-year peak, expanding 22 percent to nearly USD 420 billion, and entered a new growth phase with artificial intelligence (AI), 5G and other new technologies leading the surge with greater market segmentation, diversification and decentralization. The emergence of smart automobiles, smart cities, smart medicine, AR/VR and other new markets headed the list of new applications. In the next three to five years, semiconductor industry growth is expected to remain stable, with no marked declines. In 2018, the growth rate is expected to fall to between 5 percent and 8 percent, with the expansion more comprehensive and balanced. The memory market, in particular, will find it hard to match its 2017 blistering growth rate. The market’s expected growth of 10 percent to 20 percent will be chiefly driven by DRAM and 3D NAND Flash. In 2019, NAND growth will continue but DRAM shipments could decline. Emphasis on both innovation and investment key to sustainable growth of Chinese IC Under the China government’s Guidelines to Promote National IC Industry Development, designed to provide key policy guidance and capital support for the development of China’s IC industry, the Chinese semiconductor industry is seeing particularly rapid growth that is expected to be a key contributor to continuing global industry expansion. In IC design, HiSilicon and Unigroup Spreadtrum RDA ranked among the top 10 in the world. In wafer fabrication, Chinese IC manufacturing accounted for 13 percent to 15 percent of global market capacity despite SMIC and Huahong Group lagging international competition in advanced processing. In packaging and testing – China’s strongest segment – JCET, NFME and Huatian Technology also ranked in the global top 10. The Guidelines to Promote National IC Industry Development has fueled a boom in capital investments. However, investments must go well beyond fab construction to add new capacity for China’s semiconductor industry to flourish. A strategy for sustainable, long-term chip industry growth must focus more on technology innovation while continuing heavy capital investments, though it takes time for innovation to lead to higher capacity demand and GPD growth and more jobs. Despite large investments by the 02 Special Project in semiconductor equipment and materials, China trails other regions of the world in advanced technologies. Global spending on semiconductor equipment reached a record-breaking USD 56 billion in 2017, with Korea a major driver. In 2017, Samsung alone invested USD 25 billion in semiconductor equipment, followed by TSMC (USD 10.8 billion), Intel (USD 11.5 billion), Hynix (USD 8.5 billion), Micron (USD 0.5 billion), SMIC (USD 2.3 billion) and YMTC (USD 2 billion). In 2018, Samsung’s equipment spending is expected to drop slightly, to USD 24 billion, while investments by Intel and TSMC will be remain roughly equal. China’s equipment spending will continue to grow in 2018, with SMIC and YMTC maintaining investment levels similar to last year’s and other China semiconductor manufacturers starting to ramp up investments. In 2018, China is expected to surpass Taiwan in equipment spending to claim the number two position after Korea. SIIP China dedicated to international connection and cooperation The huge investments in China’s semiconductor industry need to be supported by robust business strategies, greater international cooperation, deeper expertise in advanced technologies, and more skilled workers. China lags the global industry in all of these areas. The rapid rise of China’s semiconductor industry has raised concerns among many countries over China’s growing influence, with some, most notably the United States, going so far as to implement containment measures. Other regions including Japan, Korea and Taiwan followed suit. The continued growth of China’s semiconductor industry hinges on technological innovation enabled by international cooperation, as well as strong international communication to allay concerns and misunderstandings over the rising prominence of China’s chip sector. China must overcome these obstacles. One partial solution is for China to convince the rest of the world that its need a thriving semiconductor industry if only to meet enormous demand for electronics products within its own borders. As the largest international semiconductor industry association, SEMI enjoys a unique ability to strengthen the connection between China’s semiconductor sector and its international counterparts. SEMI is well-known for its vital support of the traditional semiconductor equipment and materials markets, but SEMI’s work also spans IC design, manufacturing, packaging and testing. What’s more, SEMI has expanded into innovative market vertical applications such as AI, smart manufacturing, smart transportation and smart automotive as it aims to bring together supply chains across these growth areas. For its part, SEMI China remains dedicated to improving communications and cooperation between the Chinese and global semiconductor industries. SEMI China will also continue to encourage deeper collaboration among individual enterprises and government institutions in the interest of industry growth while making full use of SEMI’s international, professional and localization platform to promote the development of China’s semiconductor industry. Last year, we established SEMI Innovation Investment Platform (SIIP) China to help grow China’s pool of skilled workers, promote advanced technology, generate industry capital, and expand China’s semiconductor industry while developing stronger connections with chip sectors in other regions. SIIP China is focused on the following: Promoting sustainable development of the Chinese semiconductor industry Establishing stronger connections to help take advantage of global technology and investment opportunities Providing a platform for open communications between the Chinese and global semiconductor industries Promoting greater coordination between China and its global partners Helping newly enterprises secure funds for expansion Encouraging greater cooperation with foreign semiconductor manufacturers in the interest of openness and mutual benefit will be the best way for China to overcome obstacles to the development of its semiconductor industry. Meanwhile, China will continue to strive to merge into the global semiconductor industry and become a key partner. SEMICON China has witnessed the development of Chinese semiconductor industry SEMICON China marked its 30th anniversary this year. Over the past three decades, China’s semiconductor industry has seen remarkable growth. This year’s SEMICON China was the largest ever. SEMICON China and FPD China 2018 numbered 3,628 booths, covered 74,000 square meters of exhibition space and attracted 1,116 exhibitors from 21 countries and regions and 91,252 professional attendees from 58 countries and regions. Most of China’s top device makers and global leading packaging houses, together with their equipment and materials suppliers, exhibited at SEMICON China and FPD China 2018, representing the global IC manufacturing ecosystem. The number of SEMICON China and FPD China 2018 visitors jumped 32.3 percent from last year, with representation by professionals from the design, manufacturing, assembly and test, equipment and materials sectors. Lung Chu is President of SEMI China.