BIOGRAPHY
- Chair/Founder, Etron, eYs3D & eEver Technology Companies
- IEEE Fellow, NAE (USA) Member
- IEEE Highest Technical Award Winner in Solid-State Circuits
- Chair (2014-15), WSC (World Semiconductor Council)
- Chair (2013-17) & Board Director(1996~), Taiwan Semiconductor Industry Association (TSIA)
- Chair (2019~), AI-on-Chip Taiwan Alliance
- Chair (2009-11), Board Director & APAC Leader (2004~), Global Semiconductor Alliance (GSA)
As a researcher, engineer, inventor, design architect, serial entrepreneur and chief executive, Dr. Lu has dedicated his career to the worldwide IC design and semiconductor industry. Retentive research with creativity and high-tech corporate management drive him successful in starting up companies with innovations to public with other cofounders and coworkers, including Etron, Ardentec and Global Unichip.
Dr. Lu received his B.S. in Electrical Engineering from National Taiwan University and M.S. and Ph.D. in EE from Stanford University. He worked for the IBM Research (esp. with Dennard and Terman) and then IBM HQs (Staff & Semiconductor Program Manager for Group President and CEO) from 1982 to 1990 and won numerous IBM Innovation/Technical Achievement Awards, including an IBM Corporate Award. He invented a SPT (Substrate-Plate Trench) DRAM cell using a novel 3D trench-capacitor structure which drove innovative technologies realized in billions of ICs (e.g. trench etching and filling, Chemical-Mechanical Polishing, MeV ion-implantation, salicides, Tungsten-studs, Damascene Backend and Coppor interconnections) and created High Speed DRAM (HSDRAM) chips/circuits to revolutionize Memory’s random access speeds by 3X faster than conventional ones, which realizing the world’s first 4Mb DRAM product by IBM who later licensed to many companies making DRAMs from 4Mb to 1Gb densities and Embedded DRAMs prevailing in computers, cell phones and mobile vehicles.
He was elected as a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 1991, and in 1999 to a Member of National Academy of Engineering (NAE) of USA. Dr Lu is a recipient of the “IEEE 1998 Solid-State Circuits D.O. Pederson Award” for his leading contributions in high-speed dynamic memory design and memory cell device technology. In addition, Dr. Lu holds over 40 granted and 18 waiting US patents and has published more than 60 technical papers. He has been a Technical Program Committee Member of VLSI Symposia since 1987 and was on TPC of ISSCC (1987-2012 and won four times of Outstanding Panel Awards) and Technical Program Chair (2007) and Conference Chair (2014) of A-SSCC (Asian Solid-State Circuits Conference).
In early 1990s, Dr. Lu was a co-architect/leader creating Taiwan’s 8-inch-wafer and Advanced Logic/SRAM/DRAM technologies to equip Taiwan semiconductor industry with leading-edge technology capabilities, which has thus enabled and shaped Taiwan semiconductor and integrated circuits industries to today’s prominent position in supplying critical silicon products/wafers to support the worldwide high-tech industry and economics. Lu received the 2001 Honorary Medal of Science and Technology from the Premier for his contributions to Taiwan. Dr. Lu was elected to a Fellow (’04) and received the Scientific Management Award (’12) of Chinese Society for Management of Technology. He was given the honor of the “2007 Taiwan’s Golden Merchant Award” from General Chamber of Commerce and the “2010 ERSO Award” by Pan Wen Yuan Foundation to cite for his contribution to the Memory IC Design Industry. He was awarded an Industry Contribution Award from SEMI at 2017 SEMICON Taiwan.
Since 1999, Dr. Lu has pioneered several Known-Good-Die Memory products enabling customers’ stacked-die system chips in 3D structures. This trend summoned the new rise of an IC Heterogeneous Integration (HI) Era as raised in his plenary talk “Emerging Technology and Business Solutions for System Chips” in the International Solid-State Circuits Conference (ISSCC) in 2004. This stimulated IEEE formally to establish a Heterogeneous Integration Roadmap (HIR) in 2017 to accelerate research, innovations and collaborations across the entire ecosystem for future semiconductor industry in parallel to Moore’s Law (Monolithic Integration: MI).