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This collection contains presentations by Michael Lercel, Ph.D., Director of Strategic Marketing at ASML, Christoph Hensche, SVP Semiconductor Mask Solutions at ZEISS, and Jonathan Chang, Senior Design Engineer at Xilinx, which were given at SEMICON Japan in December 2018 in Tokyo.

“Extending Semiconductor Patterning into the Next Decade” discusses near-term challenges and solutions of patterning scaling and cost-effective EUV, as well as edge placement error and metrology. Defectivity, high volume manufacturing, holistic optimization/lithography, pattern fidelity control, and deep learning are also covered. Many graphs and charts provided.

“Solutions for EUV Mask Making” discusses the invention of EUVL in 1985 as well as the first customers and readiness of infrastructure for EUV mask manufacturing. ZEISS has already addressed many of the challenges EUV mask making faces, including defectivity, registration metrology, mask tuning, mask repair, and mask verification. Their SMT fab lab in Oberkochen, Germany is being expanded as innovation continues.

“EUV, New Technologies, and Adaptable Intelligence” discusses the need for adaptable intelligence that connects everything at a global scale. Xilinx’s Versal ACAP has multi-market applications, in cloud, wireless network, and autonomous driving. Graphs show FPGA area scaling challenges, performance and power improvements, and design co-optimization.

 

Keywords: 3D NAND, DRAM, Lithography, EUV, Defects, Deep Learning, Substrate, Materials, AI, SoC, Wireless, Autonomous Vehicles, Automotive, Transportation, Metrology, HVM, Optimization, FPGA, Patterning, Scaling, Power