SEMICON Japan 2018: Extending Semiconductor Patterning into the Next Decade

Michael Lercel, Ph.D., Director of Strategic Marketing at ASML, discusses near-term challenges and solutions of patterning scaling and cost-effective EUV, as well as edge placement error and metrology. Defectivity, high volume manufacturing, holistic optimization/lithography, pattern fidelity control, and deep learning are also covered. Many graphs and charts provided. From SEMICON Japan in December 2018 in Tokyo.

Keywords: Lithography, EUV, DRAM, Defects, Deep Learning, Patterning, Scaling, Metrology, Optimization