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As AI workloads continue to scale, gains in performance and efficiency are increasingly determined by physical design choices at the device, materials, and manufacturing levels. This technical deep dive examines how innovations in compute-in-memory architectures, two-dimensional and topological materials, photonic integration, and atomic-scale process control are reshaping the hardware foundations of AI. Drawing directly from the Future of Computing: Sustainable AI Systems workshop, the article explores the mechanisms, constraints, and manufacturing realities that govern whether these technologies can transition from research to scalable production.

 

Compute-in-Memory and Emerging Memory Devices (Micron)

Ashonita Chavan detailed how emerging memory devices enable computation closer to stored data, reducing the dominant energy cost associated with memory access.

Key device classes discussed:
•    Resistive RAM (RRAM)
•    Phase-change memory (PCM)
•    Ferroelectric RAM (FeRAM)
•    Magnetoresistive RAM (MRAM)

By embedding these devices near or within memory arrays, Micron demonstrated:
•    2.5× improvement in performance per watt
•    Reduced latency compared to DRAM-centric architectures
•    Compatibility with existing accelerator workflows
 
Technical constraints:
•    Variability and endurance across device types
•    Integration with packaging and metrology flows
•    Security considerations for in-memory execution


Analog Crossbar Arrays for AI Acceleration (IBM Research)


Geoff Burr described resistive crossbar arrays that perform matrix-vector multiplication using physical laws:
•    Ohm’s Law for multiplication
•    Kirchhoff’s Current Law for accumulation

 

This enables:
•    Direct execution of multiply-accumulate operations in hardware
•    90% reduction in data movement
•    Significant energy savings for dense linear algebra workloads

Key challenges:
•    Analog noise and drift
•    Device-to-device variability
•    Efficient handling of non-linear operations (≈5% of AI compute)

Ongoing research focuses on architectural techniques and algorithmic compensation to maintain inference accuracy.


Two-Dimensional Semiconductors and Interconnect Materials (Stanford)

 

Eric Pop presented experimental and modeling results showing:
•    Mobility preservation in MoS₂ and WSe₂ at sub-1 nm thickness
•    Viable n- and p-type operation with suitable bandgaps
•    Van der Waals bonding enabling heterogeneous stacking

At the interconnect level:
•    NbP topological semimetals exhibit inverse resistivity scaling
•    Reduced surface scattering improves performance at narrow dimensions

 

Thermal management materials such as AlN and hBN were highlighted as essential for 3D stacks.


CMOS + Photonics and 3D MOSAIC Architectures (UC Davis)


Saif Islam’s MOSAIC framework integrates:
•    CMOS logic
•    Dense memory
•    Silicon photonics
•    Ultrafast sensors

Demonstrated capabilities include:
•    100 GHz bandwidth photonic sensing
•    High quantum efficiency (>90%)
•    CMOS-compatible integration paths

These systems target AI workloads where sensing and inference are tightly coupled.


Atomic-Scale Process Engineering and Digital Twins (Lam Research)

David Fried detailed how Lam’s process technologies address escalating complexity:
•    Molybdenum metallization with ~50% lower resistance than TiN/W
•    Advanced conductor etch enabling extreme aspect ratios
•    Multi-scale digital twins spanning equipment, subsystem, and feature levels

Digital twins support:
•    Predictive process optimization
•    Reduced experimental cycles
•    Faster yield learning for novel architectures

 

Technical Synthesis

Layer

Key Innovation

Impact

Memory

Compute-in-memory

Cuts data-movement energy

Device

2D semiconductors

Enables dense 3D stacking

Interconnect

Topological metals

Reduces resistive loss

System

CMOS + photonics

Collapses sensing & compute

Process

Digital twins

Manages complexity at scale




Technical Perspective

Panelists at the "Future of Computing: Sustainable AI Systems" workshop demonstrated that sustainable AI hardware is not the result of a single breakthrough, but of co-optimization across materials, devices, architectures, and manufacturing intelligence. Each advance reduces a different bottleneck—but only when combined do they enable scalable, energy-efficient AI systems.