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Packaging Highlights

Applied Materials and Besi to jointly develop chip integration technology (Evertiq; Oct 23, 2020)

IBM Takes AI Chip Research to Next Level (RT Insights; Oct 23, 2020)

Packaging Demands For RF And Microwave (Semiconductor Engineering; Oct 22, 2020)

Power Packaging Trends And The 48V Ecosystem (Semiconductor Engineering; Oct 22, 2020)

Defect Challenges Grow For IC Packaging (Semiconductor Engineering; Oct 22, 2020)

Making Chips To Last Their Expected Lifetimes (Semiconductor Engineering; Oct 21, 2020)

10 basic terms for advanced IC packaging (EDN Asia; Oct 20, 2020)

Collective die-to-wafer bonding with sub-2μm accuracy for 3D packaging (eeNews Europe; Oct 19, 2020)

How Is Intel Part of a “SHIP” Program? (EE Times Asia; Oct 16, 2020)

DoD Awards $197M in Microelectronics Tech Dev’t OTAs (GovCon Wire; Oct 16, 2020)

Process Control and Inspection for High-Value Advanced Packages: It’s Complicated (3D InCites; Oct 15, 2020)

IFTLE 464: TSMC’s Family of Packaging Technologies Create 3D Fabric (3D InCites; Oct 14, 2020)

EDPS 2020: An Inside Look at the Manufacturing-centric Presentations (3D InCites; Oct 12, 2020)

Advanced packaging could help solve chip I/O limitations (EDN Asia; Oct 12, 2020)

Defense awards for Intel SHIP project now top $156M (Fierce Electronics; Oct 10, 2020)

3D InCites Community Members Pack the Virtual IWLPC Exhibitor Hall and Technical Program (3D InCites; Oct 8, 2020)

SkyWater to 'on-shore' packaging of chips in Florida (eeNews Analog; Oct 8, 2020)

Taking a Closer Look at Intel’s Process Roadmap (EE Times Asia; Oct 6, 2020)

Intel lands US Defense Department advanced semiconductor packaging development contract (The Burn-In; Oct 5, 2020)

System-Level Packaging Tradeoffs (Semiconductor Engineering; Sep 30, 2020)

TSMC Mulls Another Fab for 2nm & Two Fabs for Advanced Packaging (Tom's Hardware; Sep 27, 2020)

IC Packaging Technologies Contribute to Smaller, Faster, Cheaper Electronic Systems with Longer Battery Life (3D InCites; Sep 23, 2020)

KLA launches new advanced semiconductor packaging techniques (Packaging Gateway; Sep 22, 2020)

IFTLE 462: If Not a Node then What? (3D InCites; Sep 22, 2020)

48V Ecosystem and Power Packaging Trends (3D InCites; Sep 21, 2020)

Hanwha, SK hynix develop core chip packaging equipment (The Korea Herald; Sep 21, 2020)

Heterogeneous integration enables advanced IC packaging (EDN Asia; Sep 21, 2020)

How Secure Is The Package? (Semiconductor Engineering; Sep 17, 2020)

Lost in the advanced IC packaging labyrinth? Know these 10 basic terms (EDN; Sep 17, 2020)

Momentum Builds For Advanced Packaging (Semiconductor Engineering; Sep 17, 2020)

Advanced Packaging: Strong Momentum Driven by TSMC, Intel and Samsung (EE Times Asia; Sep 16, 2020)

Intel leans hard on advanced chip packaging technologies in battle for computing supremacy (VentureBeat; Sep 16, 2020)

IFTLE 461: Samsung 3D-IC X-Cube; Intel Announces Hybrid Bonding (Sep 15, 2020)

CIS packager Xintec posts record revenues for August (DIGITIMES; Sep 15, 2020)

IT Hardware Industry (9): Next-generation Post-fab Technologies Appearing (Business Korea; Sep 14, 2020)

Tighter integration between process technologies and packaging (EDN; Sep 9, 2020)

Wafer-scale micro-LEDs transferred onto adhesive film for planar and flexible displays (Semiconductor Today; Sep 8, 2020)

Intel, Samsung, TSMC to drive chip packaging forward (eeNews Analog; Sep 8, 2020)

Will fan-out wafer-level packaging keep Moore’s Law valid? (EDN; Sep 4, 2020)

5 keys to next-generation IC packaging design (EDN; Sep 4, 2020)

Heterogeneous integration and the evolution of IC packaging (EDN; Sep 2, 2020)

New Architectures, Much Faster Chips (Semiconductor Engineering; Aug 31, 2020)

Marvell Joins TSMC’s Big League Customers with 5G ICs (EE Times; Aug 27, 2020)

TSMC updates its progress on 4 nm and 3 nm technology (Electronics 360; Aug 26, 2020)

IFTLE 459: imec Develops Nano-TSV for Heterogeneous Integration (3D InCites; Aug 24, 2020)

New EDA Design Tool Addresses Heterogenous Systems Integration (Embedded; Aug 24, 2020)

Intel's Future 7nm FPGAs to Use Foveros 3D Stacking (Anandtech; Aug 21, 2020)

Moore’s Law Enters The 4th Dimension (Semiconductor Engineering; Aug 21, 2020)

ISES 2020 Highlights Asia’s Advanced IC Packaging and HI Capabilities (3D InCites; Aug 19, 2020)

US Army-funded research project makes inroads on scaling quantum processors (Defense News: Aug 17, 2020)

Intel Next-Gen 10-micron Stacking: Going 3D Beyond Foveros (Anandtech; Aug 14, 2020)

Samsung Announces "X-Cube" 3D TSV SRAM-Logic Die Stacking Technology (Anandtech; Aug 14, 2020)

The Demise of US Chip-making Accelerates as Intel Falls Further Behind (3D InCites; Aug 14, 2020)

IFTLE 458: Technologies Migrate from Both Directions to AP Processes (3D InCites; Aug 13, 2020)

DAC 2020 Addresses Chiplet Design and Integration (3D InCites; Aug 11, 2020)

SMD Package for Rad-Hard Power Electronics (EE Times; Aug 10, 2020)

AMD's next-gen RDNA 3: revolutionary chiplet design could crush NVIDIA (TweakTown News; Aug 8, 2020)

IFTLE 457: Hybrid Bonding Comes of Age (3D InCites; Aug 3, 2020)

The Global Packaging Community Shows up for Virtual ECTC! (3D InCites; Jul 29, 2020)

TechSearch Presentation Highlights Key Developments in Advanced Packaging (3D InCites; Jul 28, 2020)

Impressive turn-out for the virtual 70th ECTC (Micronews; Jul 28, 2020)Intel’s Stumble Signals AMD’s Gain (EE Times; Jul 27, 2020)

Imec sees five semiconductor trends for the 20s decade (; Jul 27, 2020)

Before SEMICON West 2020, There was IMEC ITF USA 2020 (3D InCites; Jul 23, 2020)

The Race To Much More Advanced Packaging (Semiconductor Engineering; Jul 23, 2020)

Moore’s Law Isn’t Slowing down — Just Ask System Companies (EE Times; Jul 20, 2020)

CHIPS Alliance Announces AIB 2.0 Draft Specification to Accelerate Design of Open Source Chiplets (Design & Reuse; Jul 16, 2020)

Virtual DAC 2020 Addresses Chiplets and Advanced Packaging (3D InCites; Jul 16, 2020)

CITC and HAN course taps into increasing chip packaging complexity (Bits & Chips (Jul 16, 2020)

Copper Electrodeposition For Fan-Out Wafer-Level Packaging (Semiconductor Engineering; Jul 16, 2020)

Quantum Chiplets Scale Up Spin Qubits (Optics & Photonics News; Jul 15, 2020)

3D ICs Tear Down the Dreaded Memory Wall and Save Power (3D InCites; Jul 15, 2020)

Heterogeneous integration calls for new approaches (Tech Design Forum; Jul 13, 2020)

Chiplets Promise to Revive Moore’s Law (EE Times; Jul 9, 2020)

Scaling Up the Quantum Chip (MIT News; Jul 8, 2020)

VLSI 2020: 3D Continues to Dominate Advanced Semiconductor Technology (3D InCites; Jul 6, 2020)

Social Distancing Spotlight: How KLA Keeps Looking Ahead (3D InCites; Jun 29, 2020)

Optimizing Chiplet-to-Chiplet Communications (; Jun 29, 2020)

U.S. Chip-Revival Initiative Gains Traction (EPS News; Jun 22, 2020)

An EDA Perspective on Today’s Advanced Packaging (3D InCites; Jun 22, 2020)

China Speeds Up Advanced Chip Development (Semiconductor Engineering; Jun 22, 2020)

Highlights of the day: Intel, TSMC head to head in 3D packaging (DigiTimes; Jun 18, 2020)

3D System Integration – It Takes a Village (3D InCites; Jun 18, 2020)

The Next Advanced Packages (Semiconductor Engineering; Jun 18, 2020)

Spreading Out The Cost At 3nm (Semiconductor Engineering; Jun 18, 2020)

Interconnect Challenges Grow, Tools Lag (Semiconductor Engineering; Jun 15, 2020)

Xperi and Tower Semiconductor announce new license for 3D stacked image sensor technology (i-micronews; Jun 12, 2020)

NanoResolution MRS Sensor Delivers Fast, Precise 3D Inspection And Measurement For Advanced Semiconductor Packaging Applications (Semiconductor Engineering; Jun 8, 2020)

EDA and the Heterogeneous Integration Roadmap (3D InCites; Jun 3, 2020)

IFTLE 451: Advanced Packaging is Leading Electronics into the 2020s (3D InCites; Jun 1, 2020)

Modeling, Simulation and Test for Multi-die IC Designs (3D InCites; May 27, 2020)

ASMPT well positioned to ride the next wave of Advanced Packaging in Heterogeneous Integration (DigiTimes; May 26, 2020)

Fan-Out Wafer-Level Packaging And Copper Electrodeposition (Semiconductor Engineering; May 21, 2020)

IFTLE 450: Chiplet is the New Buzzword but Disintegration is the New Technology (3D InCites; May 20, 2020)

Building 3D neural structures on a single wafer (EE Times; May 19, 2020)

IFTLE 449: Advanced Packaging and Chiplets at the IMAPS DPC (3D InCites; May 13, 2020)

An Inside Look At Testing’s Leading Edge (Semiconductor Engineering; May 12, 2020)

Temporary Wafer Bonding System Is Based On Electrostatics, Not Adhesives (3D InCites; May 11, 2020)

Chiplets: The New Era Begins (3D InCites; May 8, 2020)

System-on-Chip Disintegration is Underway (3D InCites; May 7, 2020)

Ask the Expert: Q&A with Process Engineers (EE Times Asia; May 5, 2020)

Wanted: Process Engineers Versed in Packaging (EE Times; May 4, 2020)

SemiSister Success Story: A Woman on the Edge of 3D Technology (3D InCites; May 1, 2020)

The Morphing of Electronic Product Design in the Era of Moore’s Law 2.0 (Embedded Computing Design; Apr 20, 2020)

Apple supplier Foxconn steps up semiconductor plans with deal to build a new base in Qingdao (South China Morning Post; Apr 17, 2020)

Hon Hai reportedly to build IC packaging, testing plant in China (Focus Taiwan; Apr 16, 2020)

The Story Behind Advanced Packaging, Heterogeneous Integration And Test (Semiconductor Engineering; Apr 6, 2020)

Adding New Dimensions to Power Electronics Packaging (Electronic Design; Apr 3, 2020)

How does heterogeneous integration impact sensors? (EE World Online; Mar 26, 2020)

IFTLE 444: Chip on Interposer on Substrate vs High Density Chips-Last Package Cost Modeling (3D InCites; Mar 26, 2020)

IFTLE 443: Controlling Warpage and Placement Error for FOWLP (3D InCites; Mar 23, 2020)

The G target="_blank"olden Age of Packaging Brought to you by Chiplet Integration (3D InCites; Mar 16, 2020)

An Inside Look at 3D-DfT Standard IEEE Std 1838™-2019 (3D InCites; Mar 17, 2020)

Heterogeneous Integration Technologies for Moore’s Law 2.0 and Beyond (3D InCites; Mar 12, 2020)

Grading Chips For Longer Lifetimes (Semiconductor Engineering; Mar 10, 2020)

Wafer Test Challenges For Chiplets (Semiconductor Engineering; Mar 10, 2020)

Comprehensive review of heterogeneously integrated 2-D materials (; Mar 6, 2020)

3nm: Blurring Lines Between SoCs, PCBs And Packages (Semiconductor Engineering; Mar 2, 2020)

Chiplet Momentum Rising (Semiconductor Engineering; Feb 26, 2020)

Is The HIR the Best Path to Increased Revenues? (3D InCites; Feb 25, 2020)

IFTLE 441: Will TSMC Ever Put a Chip or Packaging Facility in the USA? (3D InCites; Feb 21, 2020)

Big Data, Speed and Security Dominate DesignCon 2020 (3D InCites; Feb 12, 2020)

IFTLE 440: Copper Pillar Bump Development for 7nm Node Devices (3D InCites; Feb 10, 2020)

Researchers demonstrate ultra-flexible heterogeneous electronics (eeNews Europe; Feb 6, 2020)

SiP and Heterogeneous Integration as Key Driving Force of Growth for IC Packaging and Testing (CTIMES; Feb 3, 2020)

IFTLE 439: imec’s Flip Chip on FOWLP… a Closer Look (3D InCites; Jan 31, 2020)

Is This The Year Of The Chiplet? (Semiconductor Engineering; Jan 23, 2020)

IFTLE 438: Reliability Test For 0.3mm WLCSP; Copper RDL Trace Requirements (3D InCites; Jan 21, 2020)

Novel Multi-die Integration Concept Offers Big Benefits (3D InCites; Jan 14, 2020)

IFTLE 437: Packaging Trends for Artificial Intelligence (3D InCites; Jan 13, 2020)

SJSemi strengthens presence in wafer-level 3D packaging segment (DigiTimes; Jan 3, 2020)

Advanced Packaging is Everyone’s Business! (3D InCites; Dec 13, 2019)

IFTLE 434: Process Optimization for a Reliable NXP FOWLP Microcontroller (3D InCites; Dec 12, 2019)

IC buyers will purchase more chips housed in advanced semiconductor packages (Electronics Sourcing Online; Dec 5, 2019)

IFTLE 433: AMD Chiplets go Commercial Amidst a Need for Chiplet Standardization (3D InCites; Dec 5, 2019)

Vehicle Autonomy & Electrification Push Advanced Packaging for Automotive Applications (3D InCites; Dec 4, 2019)

Talking about Neural Networks and SoC Design Challenges (3D InCites; Dec 4, 2019)

Thermal Challenges In Advanced Packaging (Semiconductor Engineering; Dec 2, 2019)

EU Project Sets Sights on Advanced Packaging (EE Times Europe Nov 26, 2019)

Powering future optical microsystems with chip-scale integrated photonics (Nanowerk; Nov 25, 2019)

Boosting the 5G Network (Labroot; Nov 24, 2019)

SEMICON Europa and Productronica 2019 Exhibitor Showcase (Nov 21, 2019)

PTI chair sees FOPLP as alternative solution for IC scaling (DigiTimes; Nov 21, 2019)

IFTLE 431: Samsung Qualifies EDA Tools for Multi-die Integration (3D InCites; Nov 17, 2019)

Highlights of the day: TSMC, UMC to give driver IC designers more capacity support (DigiTimes; Nov 14, 2019)

Fujian, Hong Kong sign joint 5.4 billion yuan investment deal (China Daily; Nov 14, 2019)

SEMI 3D & Systems Summit to Spotlight Latest in 3D Roadmap, Heterogeneous Integration and SiP Technologies (3D InCites; Nov 11, 2019)

IFTLE 430: Exascale Computing in Europe: Leading Edge Packaging is the Key! (3D InCites; Nov 11, 2019)

3D VLSI Open Workshop Showcases 3D IC Supply Chain Capabilities (3D InCites; Nov 8, 2019)

Die attach equipment: Yole’s analysts announce a consolidation of the market (3D InCites; Nov 4. 3019)

The IWLPC Fan-out PLP Smack Down (3D InCites; Oct 31, 2019)

ASE eyes bright 1Q20 amid strong 5G-driven backend demand (DigiTimes; Oct 31, 2019)

Heterogeneous Integration ramps up electronics clout (Evaluation Engineering; Oct 28, 2019)


IFTLE 429: Samsung 12-layer memory with 3D-TSV; SHIP Winners (3D InCites; Oct 24, 2019)

Keeping an Eye on the Future (POTs and PANs; Oct 22, 2019)

Research Seeks to Improve Computers’ Energy Efficiency on Micro, Macro Levels (I-Connect007; Oct 21, 2019)

What’s The Best Advanced Packaging Option? (Semiconductor Engineering; Oct 17, 2019)

IFTLE 428: Panel Level Processing: We’ve Come A Long Way Baby! (3D InCites: Oct 16, 2019)

IWLPC 2019 Brings You Advanced Packaging in an Interconnected World (3D InCites; Oct 14, 2019)

Highlights from EDPS 2019 (3D InCites; Oct 14, 2019)

Samsung Electronics Develops Most Advanced Semiconductor Packaging Technology (Business Korea; Oct 9, 2019)

More Data, More Processing, More Chips (Semiconductor Engineering; Oct 7, 2019)

Reaping the Benefits of a Design and Manufacturing Ecosystem (3D InCites; Oct 4, 2019)

IFTLE 127: TSMC’s Next-Gen 3D Technology  (3D InCites; Oct 4, 2019)

Exhibitor Highlights at IMAPS International Symposium (3D InCites; Sep 26, 2019)

IFTLE 426: Exascale Computing is Near; Incandescent Lightbulbs get a Reprieve (3D InCites; Sep 26, 2019)

Is Fan-Out packaging still popular? (AnySilicon; Sep 24, 2019)

Driving With Chiplets (Semiconductor Engineering; Sep 24, 2019)

Making more of Moore’s Law (Evaluation Engineering; Sep 23, 2019)

The Race To Next-Gen 2.5D/3D Packages (Semiconductor Engineering; Sep 23, 2019)

Stacking Memory On Logic, Take Two (Semiconductor Engineering; Sep 19, 2019)

Is Fan-Out packaging still popular? Equipment & material companies are the heartbeats of this ecosystem (3D InCites; Sep 17, 2019)

IFTLE 425: Deca FOWLP is Going Mainstream; Highlights from Hot Chips (3D InCites; Sep 11, 2019)

EPS 2019: Imagining Thomas Edison as the Father of Advanced Packaging (3D InCites; Sep 10, 2019)

New Technologies To Support 3D-ICs (Semiconductor Engineering; Sep 4, 2019)

Advanced Packaging Options Increase (Semiconductor Engineering; Aug 19, 2019)

IFTLE  423: GLOBALFOUNDRIES and ARM Turn to 3D Chip Stacks for High Performance Computing (3D InCites; Aug 19, 2019)

ASE to buy new factory building to optimize capacity deployment (DigiTimes; Aug 13, 2019)

IFTLE 422: Is Advanced Packaging Production Returning to the US by SHIP? (3D InCites; Aug 9, 2019)

A Look Inside The 3D Technology Toolbox For STCO (3D InCites; Aug 8, 2019)

Intel Shows Off Chip Packaging Powers (IEEE Spectrum; Jul 31, 2019)

New Details About More-than-Moore Test Technology Advances (3D InCites; Jul 31, 2019)

IFTLE 421: Intel Showcases Co-EMIB Advanced Packaging Architecture (3D InCites; Jul 30, 2019)

Memory Dominates Semiconductors, Driving Packaging (Forbes; Jul 21, 2019)

Chip Stacks Hit Semicon Spotlight (EE Times; Jul 12, 2019)

Intel unveils new 3D chip packaging design (Network World; Jul 10, 2019)

SiP Technology To Enable Technology Megatrends (3D InCites; Jul 2, 2019)

Good News about Glass Substrates (3D InCites; Jun 24, 2019)

IFTLE 417: Passing the Advanced Packaging Baton to TSMC’s 3D-MiM (3D InCites; Jun 20, 2019)

What’s Next In Advanced Packaging (Semiconductor Engineering; Jun 20, 2019)

Power, Reliability And Security In Packaging (Semiconductor Engineering; Jun 19, 2019)

Fan-out Panel-level Packaging Comes to the ECTC Technology Corner (3D InCites; Jun 12, 2019)

ECTC Packaging Trends (Semiconductor Engineering; Jun 10, 2019)

Moore’s Law is Dead (Again), Chiplets are Hot, and other Highlights of ECTC 2019 (3D InCites; Jun 4, 2019)

IFTLE 415:Substrate-like PCBs; Three Top Ten Packaging Houses are China-based (3D InCites; Jun 1, 2019)

Asian Edge: The big advance of the Chinese IC packaging and testing industry (DIGITIMES, May 15, 2019)

Chiplet Momentum Builds, Despite Tradeoffs (Semiconductor Engineering; May 13, 2019)

U2U 2019 Conference Dives into 2.5/3D IC Design (3D InCites; May 13, 2019)

IFTLE 413: Beware of Technology Hype for the Automotive Market (3D InCites; May 10, 2019)

ITFLE 412: Samsung Discusses Packaging for the 4th Industrial Revolution; Yole looks at Non-TSV Options (3D InCites; May 6, 2019)

ECTC 2019 Will Go Back to Basics to Plan for the Future of Microelectronics and Packaging (3D InCites; May 6, 2019)

IFTLE 411: Focus on the Sensor Technology Market (3D InCites; Apr 25, 2019)

Inspecting IC Packages Using Die Sorters (Semiconductor Engineering; Apr 18, 2019)

Moore’s Law Now Requires Advanced Packaging (Semiconductor Engineering; Apr 18, 2019)

Update on 3D X-ray and DBI Technology for Advanced and 3D Packaging (3D InCites; Apr 16, 2019)

IFTLE 410: ST Microelectronics Bets on SiC; A Look at Power Device Packaging (3D InCites; Apr 15, 2019)

Advanced Packaging Bringing Semiconductor Revolution (eeDesignIT; Apr 8, 2019)


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