Microelectronic Cooling Advancements Through MEMS Processing
ABSTRACT
Higher performance chiplet and advanced packaging technologies are driving thermal management requirements with heat spreading and heat removal emerging as a critical focus topic. A combination of advanced chiplet technology node (scaling down of device dimensions),increases in operating frequencies and the integration of more chiplets in close proximity such as with 3D stacking and advanced packaging technologies, the adequate cooling of these integrated compute and memory chiplets is becoming increasingly difficult.
As power densities become higher, both at the chip and rack level, there has been increased interest in direct liquid cooling both for its superior efficiency and high cooling capacity. More advanced cooling solutions are also needed for thermal management aligned to product application and form factor needs, Advances in MEMs processing technology, such as deep reactive ion etching of silicon combined with fusion or hybrid bonding, may offer the opportunity to fabricate even higher aspect ratio microchannels and manifold structures.
IBM has previously demonstrated cooling over 500 W/cm2 in single chip modules using Indium to attach a 60 micron pitch microchannel to the back of a thermal test die in a single chip module. In more recent work, we have demonstrated large form factor 300 mm wafer scale microchannel cooling with a junction temperature rise of less the 18 oC with about 14 kW of dissipated power where the microchannel wafer was attached to the thermal test wafer with a solder layer. In this application, a uniform power density and a wafer junction temperature rise of 65 oC, a maximum wafer power of 76 kW could be cooled ( over 1 kW for each of the 74 chip sites on the wafer). Optimization of the microchannel design will be discussed to achieve high thermal efficiency. The cooling performance, and maximum power densities cooled, could be substantially improved if the microchannels were formed directly on the back surface of the processor chips or wafers. This presentation, with a focus on adopting standard MEMS and CMOS manufacturing practices, illustrates how an efficient cooling approach may become a strategic MEMS & Semiconductor convergence opportunity.
BIOGRAPHY
Dr. Knickerbocker is an IBM Distinguished Engineer and member of IBM Academy. He is a technical executive within IBM Research for Semiconductor & Advanced Packaging Technology with focus on Chiplet & Heterogeneous Integration Technologies for Hybrid Cloud, AI and Systems applications. He received his PhD degree in 1982 from the University of Illinois studying materials science & engineering.
He has 20 years' experience at IBM Microelectronics in packaging development and technology transfer into manufacturing for IBM and client products. He also has 20 years’ experience at IBM Research leading next generations of packaging technology including: 2D, 2.5D and 3D technology, healthcare precision sensors and precision diagnostic technology, developing miniaturization technology, heterogeneous integration & testing technology and fine pitch, multi-chip integration and test technologies for Artificial Intelligence (AI) computing solutions. Applications leveraging these materials, processes, equipment and research advancements have included: high performance micro-electronic systems such as secure, hybrid cloud, Generative AI computing, Quantum computing and Systems applications. The design, architecture, fabrication, assembly, and test have advanced fine pitch I/O, assembly and test, multi-chip heterogeneous integration technology for AI Systems, to provide advanced machine learning with advanced algorithms, training and inference to predictive insights. His advancements in packaging and collaboration between IBM and Client teams have led to 100’s thousands of high-performance modules / products shipped and over a billion wireless components / products shipped.
Dr. Knickerbocker has authored or co-authored over 400 patents / patent applications and more than 100 technical papers, presentations, and publications. He has over 18 years of participation with the Packaging Technology Committee through the Electronic Components and Technology Conference (IEEE).