Based on the SEMICON West session “Large-Field Lithography Tools for Dense Package Interconnects on Panels”
Large-field lithography emerged as a focal point in the Advanced Imaging sessions, reflecting the industry’s accelerating shift toward panel-level packaging and larger form factors. These trends challenge long-standing assumptions about lithographic tradeoffs between resolution, depth of focus, and throughput.
Speakers described how next-generation lithography platforms are being reimagined to support advanced packaging—not by maximizing a single metric, but by optimizing the system as a whole to deliver manufacturable performance at scale.
Panel-Level Packaging Reshapes Imaging Requirements
Unlike traditional wafers, panel-level substrates introduce warpage, deformation, and topographical variation that demand more adaptive imaging approaches. Lithography systems must maintain overlay accuracy and pattern fidelity across large fields of view while accommodating real-world substrate variability.
Several presenters noted that success increasingly depends on robust, tolerant imaging solutions rather than extreme high-NA designs alone. Depth of focus, alignment strategies, and process windows now carry equal weight in determining yield outcomes.
Tool Design Becomes a System-Level Optimization
Large-field lithography decisions ripple downstream into plating, etching, assembly, and test. As a result, tool design is increasingly evaluated through a holistic lens—balancing cost, throughput, yield, and integration rather than isolated optical performance. This system-level mindset reflects a broader industry shift toward co-optimization across the packaging value chain.
Why It Matters
- Panel-level packaging is essential for scaling AI hardware
- Imaging tools must tolerate real-world substrate variability
- Balanced system design outperforms single-metric optimization
What to Watch
- Adoption of lithography platforms optimized for panel formats
- Hybrid imaging strategies balancing resolution and depth of focus
- Closer integration between lithography and downstream process design
Source: “Afternoon Session: Building and Scaling AI: From Design to Productization,” SEMICON West 2025. Speakers: Ravi Mahajan (Intel); William Chen (IEEE EPS); PR Chidambaram (Qualcomm); C.P. Hung (ASE); Tim Lee (Boeing & IEEE); Ming Li (Lam Research); Jeff Pettinato (Intel Corporation). Panel moderator: Audrey Charles (Lam Research). Panelists: C.P. Hung (ASE); Tim Lee (Boeing & IEEE); Jeff Pettinato (Intel Corporation); Ming Li (Lam Research); PR Chidambaram (Qualcomm).
