ADVANCED PACKAGING SUBSTRATE TECHNOLOGIES FOR HETEROGENOUS INTEGRATION
ABSTRACT
Advanced packaging is enabling unprecedented levels of integration, enabling dense interconnection of logic, memory and optical chiplets, to create a system in a package. In AI & data centric applications, the amount of silicon content in a single package is increasing dramatically every generation. To meet future scaling, high speed signaling and power delivery needs, the package substrate must also evolve significantly. In this talk, we will cover some of the recent advances in the EMIB package platform including multiple scaling vectors such as die to die interconnection pitch, package form factor and the introduction of a bridge with TSV to enable denser and more efficient integration on package. Further, we will also cover the Intel’s latest breakthrough’s in glass core substrates which have superior mechanical, physical and optical properties and can drive dramatic improvements in chiplet integration on a substrate.
BIOGRAPHY
Rahul Manepalli is an Intel Fellow, Vice President, Director of the Substrate Packaging TD organization in Intel. He is responsible for advanced substrate packaging for all Intel’s products including research and development on panel level packaging in the company’s two internal R&D fabs. He and his team are driving the development of materials, processes and equipment for the next generation of substrate and panel level packaging technologies. His team has been the driving force behind many of the technology innovations in Intel’s Embedded Multi-die Interconnect Bridge (EMIB), Panel ODI and Glass core substrate technologies. Over his 25-year career at Intel, Rahul has also had an instrumental role in leading Intel’s assembly materials development and pathfinding efforts leading to several innovations in encapsulants, thermal interface materials and solder alloys. Rahul is the author of over 250 patent publications in semiconductor packaging, over 50 technical papers and invited talks. He has a Ph.D. in Chemical Engineering from the Georgia Institute of Technology