AFFORDABLE EUV LITHOGRAPHY SUPPORTING LOGIC AND DRAM ROADMAPS INTO THE NEXT DECADE
ABSTRACT
Semiconductor industry continues to pursue Moore`s law by printing all complex layers on a chip in the most affordable way. In the last decade EUV has played a significant role in this and has reached high-volume manufacturing maturity providing a solid foundation for continued innovation. Development on current EUV platform is focused on improvements in productivity, overlay and ultimately edge placement errors. The latest generation 0.33 NA system, the NXE:3800E, enables 38% improvement in productivity and 13% in overlay and in the next years several additional improvements are planned to provide cost effective solutions for the 2 and 1.4 nm node.
With the critical pitches in logic and DRAM scaling beyond the single exposure limit of 0.33 NA, there is a window of opportunity for single exposure High NA. This technology, currently accessible in the imec ASML High NA EUV lab, provides a significant step in resolution and contrast. The system capability enables lowering patterning costs by 20-35% for critical layers compared to 0.33 NA, by dose reduction, enabling single exposure and 1.5 or 2D layout designs for metal interconnects (e.g. corners or jogs in metal lines).
In the future both 0.33 NA and 0.55 NA EUV systems will coexist to provide solutions for economically viable critical exposures. To support the long-term technology roadmap, we developed a >10-year EUV roadmap focused on affordable scaling. The key elements in this roadmap are the improvements in system architecture and stage performance, the improvements in source power and significant steps in optics transmission. These enhancements will be deployed on a high productivity common platform for 0.33 NA, 0.55 NA and will allow potential introduction of hyper NA on the same platform.
BIOGRAPHY
- Head of Product Management EXE since April 1st 2023
- Product Management in EXE (started April 2020)
- Head of Node Transition Projects and Application Engineering
(Started September 2025) - Various roles in business line Applications as Product Manager:
YieldStar 350 introduction, Process Control SW products in Imaging and Overlay between 2010 and 2015 - Started at ASML in 2008 in Metrology & Application Development
- Imec – Lithography & Metrology engineering
- Engineering degree in Electronics from University of Leuven, Belgium