Enabling High-density Heterogeneous Integration using Wafer-scale Chiplet Reconstitution Technology
ABSTRACT
Chiplet-based packaging solutions are key to enabling power-efficient performance. With the increase in the number of chiplets in a package, it becomes challenging to achieve near-monolithic integration. Wafer-level packaging techniques can help in tackling this challenge by enabling reduced chiplet-to-chiplet interconnect lengths and increased interconnect density. Therefore, we present a wafer-scale chiplet reconstitution technology that utilizes low-temperature (100 ºC) silicon dioxide to encapsulate a dense array of closely spaced chiplets, thereby enabling high-density heterogeneous integration. The use of silicon dioxide as an encapsulant offers several advantages such as low-loss dielectric properties, reduced die-shifts or misalignments and compatibility with standard silicon processes, which allows for post-processing of the chiplets using conventional CMOS processes. This blurs the lines between package processing and silicon processing, making it a highly desirable feature of silicon dioxide as an encapsulant material. The fabrication testbed comprises of a dense array of 150 µm x 150 µm passive chiplets that are 10 - 30 µm-thick with a chiplet-to-chiplet gap ranging from 10 - 50 µm. To ensure complete chiplet encapsulation and near-monolithic integration, a test structure is designed which determines the minimum chiplet-to-chiplet gap required for a specific chiplet thickness. We have also developed techniques to transfer extremely thin (< 50 µm) reconstituted silicon dioxide tiers for post-processing (fabrication of redistribution layers) after encapsulation. Finally, we have demonstrated the ability to fabricate high-density vertical interconnects (through-oxide-vias) with via diameters ranging from 2 - 5 µm and pitches ranging from 4 - 15 µm. This leads to a > 10x increase in interconnect density as compared to conventional epoxy-based fan-out wafer-level packages.
BIOGRAPHY
Ashita Victor received her B.E degree in Electrical and Electronics Engineering from M.S. Ramaiah Institute of Technology, Bengaluru, India in 2021 and received her M.S. degree in Electrical and Computer Engineering from the Georgia Institute of Technology in 2023. She is currently pursuing her Ph.D. at the Georgia Institute of Technology under the supervision of Dr. Muhannad S Bakir. Her research is focused on developing wafer-scale packaging techniques for high-density heterogeneous integration of chiplets.