downloadGroupGroupnoun_press release_995423_000000 copyGroupnoun_Feed_96767_000000Group 19noun_pictures_1817522_000000Member company iconResource item iconStore item iconGroup 19Group 19noun_Photo_2085192_000000 Copynoun_presentation_2096081_000000Group 19Group Copy 7noun_webinar_692730_000000Path
Skip to main content

brian coppa

Brian Joseph Coppa, Ph.D. has nearly two decades of microelectronics industry experience from Micron/Intel, ASM, Tokyo Electron and EMD Electronics/Merck KGaA, Darmstadt, Germany; as a consultant to numerous other companies across the supply chain. He has authored over 15 US and foreign patent publications and numerous technical journal articles, which have received many prestigious citations globally. Most notably, he co-patented the 1st self-aligned double patterning (SADP) used in production for IC shrinks & developed the key enabling atomic layer deposited (ALD) spacer process. SADP has been critical over the last 2 decades for the semiconductor industry roadmap to continue microchip scaling. Brian is a Senior Member of the Institute of the Electrical and Electronics Engineer (IEEE) Society and has been part of the leadership team for SEMI Standard Americas Smart Manufacturing Council since its inception in 2018. Most recently, Brian now has a lead business development engineering role with ULVAC focused primarily on leading-edge semiconductor process innovation & engagement strategy. His specialties in smart manufacturing include: predictive & preventive maintenance, fault detection, digital twins and advanced process control solutions to improve overall equipment efficiency (OEE) and performance.

 

  

Return to GSMC Webpage