BIOGRAPHY
Praneetha Poloju an expert in Si Manufacturing flows from early customer engagement, design drop to Tapeout, Die prep & Assembly flows for various Si Technologies, and background in CMP (Copper / Tungsten) Si Process for various Si technologies.
Prior to joining Microsoft, she spent at Intel as MPS Foundry Lead, identified the current gaps, helped set strategy and technical preparedness with respect to MPS flows for IFS (Intel Foundry Services) and other business teams such as IP Strategy group, Intel Labs, Technology development, University program.
Prior to Intel, she worked at Globalfoundries for 7 years leading large portfolio projects under VP Design Enablement, then moved on to lead strategic direction for Business Unit - Automotive, Aerospace & Defense. Enabled customers with no touch engagement via some web / cloud-based tools implemented such as PPA tool (Power, Performance & Area) for various Silicon Technology nodes/geometries. She led joint development alliances to name a few, Efabless & Google Silicon team, launching PDK and IP reference flow in cloud with Synopsys. Successfully led DFM (Design for Manufacturability) defect and NPI risk assessment data migration to cloud within semiconductor R&D operations.
She spent over 8 years working as Research Staff Member, Advanced CMP (Chemical Mechanical Planarization) at IBM TJ Watson Research center and then as Defectivity D0 Lead at IBM’s 32nm R&D facility. Lastly a year as Process Integration lead at Micron DRAM manufacturing facility.
An Electrical engineering graduate with a few papers published with MRS, SPIE, IEEE, Patents related to CMP. Outside work she is an active volunteer with Middle & high school STEM programs, SWE (Society for Women Engineers) Judge.