BIOGRAPHY
Pady Kannampalli works in Digital Software Engineering in the Teradyne Architecture group, with a focus on semiconductor test software. He has been with Teradyne for over two decades and has architected scalable, performance-critical, and feature-rich software for Teradyne ATE instrumentation and test platforms, including a patent-pending solution for ATE. In his current role, Pady leverages expert system and AI/ML technologies to accelerate the migration of devices to high-volume manufacturing, while improving quality and minimizing the cost of tests. He is a member of, or has contributed to, Semi and IEEE standards efforts, such as TEMS, RITdb, Heterogeneous Integration Road map, 1149.10, and holds a master's degree in Computer Engineering, with a concentration in data sciences, from the University of California, Riverside.
He is a Recipient of the Teradyne Innovation award for realizing high-protocol scan instrumentation for ATE.