Substrate Engineering as the Enabler of CMOS and More than Moore at Scale
Abstract
The history of semiconductor progress demonstrates that step function improvements in system capability have often been enabled by substrate level innovation rather than transistor scaling alone. Silicon on Sapphire provided early proof that dielectric isolation could fundamentally improve radiation tolerance and then RF performance robustness and parasitic control establishing the conceptual foundation for Silicon on Insulator technologies. Subsequent advances such as Trap Rich SOI extended these benefits by engineering the handle wafer to suppress substrate coupling and enhance linearity and breakdown enabling new generations of high-performance RF and mixed signal CMOS. In each case these technologies were pioneered by startups willing to accept manufacturing and supply chain risk while larger incumbents delayed adoption until performance advantages were unequivocal. You could say something about wafer bonding and layer transfer enabling imagers as another CMOS extension of Si, and those techniques feed directly into MEMS.
As traditional CMOS scaling slows the industry has increasingly turned to More than Moore approaches integrating sensing actuation power handling and signal conditioning alongside logic. However, many of these heterogeneous systems, particularly MEMS, remain constrained by substrate architectures originally optimized for either bulk silicon or isolated device fabrication. This has limited their ability to scale in performance reliability and integration density in a manner analogous to historical CMOS trends.
Cavity Silicon on Insulator (CSOI) represents a critical enabling technology for this next phase of convergence. By selectively removing the buried oxide beneath active regions Cavity SOI introduces localized mechanical freedom, thermal isolation stress relief, and electrical decoupling while preserving planar SOI manufacturability and CMOS compatibility. In doing so it enables MEMS devices to be architected with the same substrate-driven rigor that once transformed CMOS performance.
More broadly the combination of substrate techniques including dielectric isolation, defect engineering, cavity formation, and localized substrate modification creates a new design space in which MEMS and CMOS can coexist and co-evolve on a common platform. This convergence allows heterogeneous systems to regain Moore like trajectories at the system level even as transistor level scaling slows. The paper argues that such integrated substrate architectures are foundational to the next generation of More than Moore technologies enabling scalable electromechanical switching sensing and mixed domain integration that were previously impractical using conventional approaches.
This work reviews the historical evolution of substrate engineering from Silicon on Sapphire through modern Silicon on Insulator variants examines parallels between CMOS and MEMS development paths and outlines how their convergence is now enabling new classes of integrated technologies at the intersection of electronics and mechanics.
BIOGRAPHY
Seena Partokia is the Founder and Chief Executive Officer of Cenfire, a MEMS switch company formed to commercialize a switching architecture originally developed at the Atomica MEMS foundry. Cenfire is developing a new class of silicon-based switching devices designed to deliver ultra-low power consumption, high reliability, and fast switching speeds for demanding applications across semiconductor test, AI infrastructure, automotive, aerospace, and defense.
Seena has spent his entire career focused on switching technologies across multiple semiconductor platforms. He began in the RF semiconductor industry developing switches built on Silicon on Sapphire (SOS) and Silicon on Insulator (SOI) technologies, where he gained deep experience in device physics, RF performance, and substrate engineered processes. He later transitioned into the power semiconductor space, working on high voltage devices and system level reliability challenges before becoming involved in the development and commercialization of MEMS relay technologies.
Across RF, power, and MEMS platforms, Seena’s work has consistently focused on translating advanced device architectures into manufacturable semiconductor technologies. His experience spans device design, process integration, and scaling switching technologies from early concept through high volume production environments.