March 31, 2021
Time
10:00 am - 11:00 am
Location
United States
Device scaling has brought about a great increase in the diversity of materials used in semiconductor fabrication. While planar (horizontal) scaling continues to drive great improvements in device density and performance, it has been joined by vertical scaling, adding to the palette of options in the race to develop novel architectures, particularly around device memory.
2DNAND is giving way to 3DNAND, with 3DNAND structures reaching and exceeding 100 layers. This, in turn, creates new challenges for fab equipment, processes, and the materials used to form these novel structures. In this webinar, we will explore trends in material requirements for new generations of device architecture, with special focus on the evolution of 3DNAND devices and the impact of the 3rd dimension on these materials. Mark Thirsk, Managing Partner of Linx Consulting, will address trends impacting the overall materials industry and discuss the significance of 3DNAND to the materials market. He will be followed by Scotten Jones, Founder and President of IC Knowledge, who will review the evolution of 3DNAND devices and the impact of these devices on key materials.
Agenda
Structure and Evolution of Materials Landscape and Importance of 3DNAND
The continued strong growth of the semiconductor industry has led to increased demand for wafer fab materials. This talk will assess relevant trends impacting key materials segments, overall wafer fab materials landscape. It will also review key suppliers and importance of 3DNAND to the overall materials industry.
The Evolution of 3D NAND and the Impact on Materials
Over 90% of NAND bits shipped today are fabricated with a 3D NAND process. 3D NAND is evolving with structural and material changes that will have significant impact on the material types and usages. 3D NAND has two major approaches in production: Floating Gate, a gate-first process with an oxide/poly memory stack was introduced by Intel-Micron, and continues to be used by Intel with SK Hynix set to take over from Intel. And, Charge Trap, a gate-last process with an oxide/nitride stack is in use at Kioxia, Micron, SK Hynix, Samsung, and others. Charge trap uses tungsten as the replacement word line material after etching out the nitride in the memory stack, whereas Floating gate uses poly that is retained as the word-line from the original memory stack. In addition to these high-level distinctions, changes in the placement of the peripheral CMOS, slot fill, word line and channel materials and others will all impact the materials needs. In this talk I will present the 3D NAND family tree and explore the structural changes by company and time, and the impact on material types and usage.
Q&A + Audience Input
EMG Overview & Wrap up
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