ESD Alliance Webinar: Gen-AI for Chip Design and Security

Designing functionally correct, high-performance, and provably secure system-on-chips (SoCs) has become a strategic imperative for modern computing infrastructure. Yet traditional design and verification methodologies are increasingly strained by escalating complexity, massive design scales, heterogeneous integration, and rapidly evolving security threats. Ensuring correctness, scalability, comprehensiveness, and adaptability across the full SoC lifecycle now exceeds the practical limits of conventional toolchains and human-centric workflows.

The emergence of large language models (LLMs) introduces a transformative opportunity for SoC design automation. Beyond natural language understanding and code generation, advanced LLMs demonstrate capabilities in architectural reasoning, specification refinement, vulnerability analysis, and design-space exploration. However, monolithic models alone are insufficient for the multidisciplinary and iterative nature of chip design. An agentic paradigm—where specialized LLM-driven agents collaborate within a coordinated framework—enables modular reasoning, cross-layer verification, security validation, and adaptive decision-making throughout the design process.

This talk will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification. The framework integrates design synthesis, threat modeling, formal reasoning, runtime monitoring strategies, and hardware–software co-verification into a cohesive workflow. Looking ahead, such agentic systems point toward a future of self-optimizing, security-aware, and continuously verified silicon—where AI-driven design environments not only accelerate innovation but also fundamentally redefine how we conceive, build, and trust next-generation microelectronic systems.