From Concept to Reality: Advancing Digital Twins in Semiconductor Manufacturing

This session will explore the critical data requirements for creating and maintaining digital twins. Integrating multi-modal data sources (sensors, enterprise systems, equipment, etc.) that feed into digital twins, ensuring that they accurately reflect their physical counterparts is a minimum necessity. This session will also cover data integration techniques (from various factory systems), and interoperability to support dynamic digital twins.

This session will focus on the importance of data standards for digital twins in semiconductor manufacturing, particularly in the context of dealing with unclean factory data. It will explore the challenges associated with unclean data and discuss strategies for cleaning and standardizing to ensure seamless ingestion into digital twins at various levels. Best practices for data validation, transformation, and integration as well as how to implement robust data standards to enhance reliability and accuracy of digital twins.

Sponsored by - Seeq

New patterning technologies will be needed to advance the device roadmap to 2 nm and beyond. Minimum pitch scaling will be exceptionally difficult to achieve at these advanced nodes, even with EUV patterning. Stochastic effects using wet resists during EUV patterning become problematic at the nanoscale, and can lead to line collapse, bridging, unacceptable line edge roughness (LER) and line width roughness (LWR). These stochastic effects present challenges when optimizing the tradeoffs between EUV resist resolution, dose, sensitivity, line edge / line width roughness, defectivity and cost.
In this talk, we will review the basics of dry resist technology, including dry resist equipment requirements, process flows and process integration modeling. In addition, we will present data that documents the advantages of dry resist technology over wet resist technology, demonstrating superior image quality, scaling and yield. We will conclude the talk by demonstrating a digital twin of the process integration and usage of optimization to achieve improved LER/LWR characteristics.

This session will explore the integration of digital twin technology in modeling high complexity semiconductor processes. As the semiconductor industry advances, the need for precise and efficient modeling techniques becomes crucial. Digital Twins offer a transformative approach to simulate and optimizes these processes, though challenges exist. Cases studies and future innovations will also be covered in this session.

Integrating AI/GenAI & Digital Twins - Explore the cutting-edge integration of Generative AI (GenAI) and Artificial Intelligence/Machine Learning (AI/ML) in the creation and evolution of digital twins. This session will delve into how GenAI & AI/ML technologies are revolutionizing the simulation, prediction, and real-time replication of physical assets in semiconductors through case studies and practical applications. 

The rise of sophisticated AI tools, including generative AI, is revolutionizing the semiconductor industry by enabling the analysis of vast datasets to generate valuable insights. Executives in the sector see generative AI as a transformative force rather than just another tool. They believe it can deliver significant value, particularly in manufacturing, operations, and maintenance, its potential for process and equipment analysis, Predictive maintenance and smart diagnostics.

As fabs adopt smart manufacturing and virtual modeling it is pertinent for digital twins to leverage technologies like generative AI for data generation, Data Synthesis/Augmentation, Real Time Analysis, Model Optimization (AI enhanced physics models) , Rapid Prototyping and Accelerated Design and Development with data-driven model-based learning.