Empowering AI through Advanced Packaging for Chiplet and Heterogeneous Integration
ABSTRACT
Chiplet-based heterogeneous integration has become essential for advancing power-efficient AI, HPC, and edge computing, offering benefits in yield, IP reuse, performance, and cost. Advanced packaging technologies such as 2.5D silicon TSV interposers, fan-out RDL interposers, and 3D hybrid bonding are key enablers to meet growing demands for higher bandwidth, lower power, and improved scalability.
This talk introduces Vertically Integrated Packaging (ViPack) solutions and a holistic Integrated Design Ecosystem (IDE) that together enhance design flexibility and manufacturability across advanced packaging platforms—driving innovation and accelerating the next generation of AI technologies.
BIOGRAPHY
Dr. Lihong Cao is Sr. Director, Engineering & Technical Marketing at ASE, with responsibility for driving advanced packaging technology development, package architecture for chiplet integration, technology promotion, new product introduction, strategic planning, and business engagement. Lihong has a proven track record of successfully leading engineering operations to bring up advanced System-in-Package production and chiplets integration. Her expertise spans across design, process development, and production enablement.
Prior to joining ASE, Lihong served as a Senior Manager at AMD, leading advanced packaging technology qualification worldwide for over sixteen years. She was also responsible for 2.5D packaging technology development and led AMD advanced packaging and assembly process qualifications for cross-over for all new products. She has published more than 70 papers. Lihong received a Ph.D. in Material Science & Engineering from Wuhan University of Technology, prior to completing tenure as a Research Associate Professor at Nanyang Technology University in Singapore.