Advanced Logic Device Architectures - Challenges & Solutions in Materials Metrology
As the semiconductor industry advances toward nodes below 2nm, innovations in logic device architectures—such as Gate-All-Around (GAA), Forksheet, and Complementary FETs (CFETs)—are accelerating the transition to increasingly complex 3D structures and novel material systems. These advancements present a multitude of challenges in materials engineering, including precise control of composition, doping, strain, and interfaces across a wide variety of emerging metals, dielectrics, and two-dimensional materials. Metrology solutions must now resolve critical properties at the atomic scale and bridge the gap between laboratory precision and high-volume manufacturing robustness.
This presentation will highlight the material-driven challenges in process integration and device scaling and review the spectrum of materials metrology technologies—such as SIMS, XPS, Raman and additional approaches—required for process control. Real-world case studies in nanosheet GAA and CFET flows will illustrate how state-of-the-art metrology enables accurate measurement of dopant concentrations, interface compositions, layer thicknesses, and strain evolution. Finally, the talk will survey the path from lab-to-fab metrology innovation, emphasizing how advanced in-line solutions and hybrid modeling are essential for meeting future device performance and yield requirements at the atomic scale.
BIOGRAPHY
Dr. Ganesh Vanamu is an accomplished semiconductor technologist. He currently serves as Director of Strategic Marketing at Nova Ltd., where he leads efforts to solve critical metrology challenges for advanced technology nodes (20A and below). With a Ph.D. in Chemical Engineering from the University of New Mexico, Dr. Vanamu brings over 16 years of experience driving innovation in semiconductor process technology. Passionate about bridging science and manufacturing, Dr. Vanamu holds a unique perspective on the intersection of process technology, metrology solutions, and data-driven manufacturing.
Prior to Nova, Dr. Vanamu spent more than a decade at Intel Corporation, where he held senior engineering and management roles across dry etch, thin films, and deposition. He successfully scaled processes from R&D to high-volume manufacturing at leading-edge nodes (including EUV), improved yield and reliability, and guided cross-functional teams in developing next-generation semiconductor technologies. His leadership was recognized with multiple Intel divisional and departmental awards for breakthroughs in EUV process integration, virtual endpoint etching, and productivity enhancements.
Dr. Vanamu has authored more than 20 publications in leading journals and conferences, with contributions spanning epitaxial growth, nanoscale materials, and process modeling. He is also a named inventor on patents in semiconductor processing and metrology.