Enabling Quantum Computing Through Advanced Packaging
Quantum computing is rapidly approaching an inflection point, with emerging roadmaps projecting orders-of-magnitude increases in qubit counts over the next decade. This acceleration is expected to unlock transformative capabilities across high-value applications including machine learning, materials discovery and cryptography. However, realizing scalable, fault-tolerant quantum systems is fundamentally a system integration challenge, where advanced packaging plays a central role.
Quantum systems are unlike anything in classical computing, and no single qubit modality has emerged as dominant - superconducting, trapped ion, silicon spin, photonic, and neutral atom platforms each impose distinct requirements on materials, interfaces, and interconnect technologies. These platforms must operate in extreme environments, from millikelvin temperatures to ultra-high vacuum, all while maintaining coherence and minimizing noise. Successful scaling of these systems requires seamless integration of cryogenic control electronics (cryo-CMOS), quantum devices, photonics, and room-temperature classical processing. Consequently, 3D heterogeneous integration (3DHI) has emerged as a vital tool, enabling the co-packaging and interconnection necessary for exponential qubit growth.
In this talk, we will discuss how advanced packaging must evolve well beyond conventional semiconductor paradigms to support quantum systems. This includes developing cryogenic-compatible materials with ultra-low outgassing, integrating superconducting interconnects (TSVs, micro-bumps, and wiring), and enabling high-density photonic connectivity with minimal loss. In parallel, assembly processes such as dicing and bonding must advance to enable 1um gap between neighboring die. Finally, reliability frameworks must also be redefined, as quantum systems operate under fundamentally different conditions than traditional electronics. Ultimately, scalable quantum computing depends as much on packaging and system integration as on qubit performance, positioning advanced packaging as a key enabler for transitioning quantum technologies from laboratory prototypes to manufacturable systems.
BIOGRAPHY
Pooya Tadayon is VP and Sr Fellow of Advanced Packaging at GlobalFoundries. His focus is next generation packaging technologies for photonics, quantum computing, and 3DIC. Prior to joining GlobalFoundries, Pooya was VP of Packaging and Test at Ayar Labs, and before that he spent 26 years at Intel Corporation where he was an Intel Fellow and Director of Assembly & Test Pathfinding. In that role, he was responsible for driving Intel’s advanced packaging and test roadmap, with a focus on enabling 2.5D/3D ICs, assembly/test solutions for co-packaged photonics, and novel interconnect and thermal technologies for use in test and system applications. He holds 72 patents, with more than three dozen pending, spanning the fields of test interconnect technology, thermal technology, and package/product architecture. Pooya holds a BS in chemistry from the University of Washington and a PhD in physical chemistry from Oregon State University.