Interconnect Scaling—Materials, Processes and Integration Challenges and Solutions
Advancements in metallization and interconnect technology are at the heart of driving performance, power efficiency, and scaling in modern semiconductor devices. From a wafer processing equipment supplier’s perspective, this talk will explore the evolution of materials and processes enabling next-generation interconnects. It will cover inflections in metals from copper and tungsten to cobalt, ruthenium, molybdenum, as well as changes in process integration. By bridging material science, process development, and equipment engineering, as well as the growing use of AI and digital twins, this talk will cover how collaboration across the semiconductor ecosystem is vital to achieving the performance, manufacturability, and sustainability required for future advanced nodes.
BIOGRAPHY
Anand Murthy is the Vice President of Advanced Technology Integration within the Office of the CTO at Lam Research Corporation. Anand manages various process technology initiatives in Logic, Memory and 3DIC with several research consortia fostering strong integration and collaboration. Prior to joining Lam in 2024, Anand was an Intel Fellow with over 28 years of technical and leadership experience in advancing Moore's law of transistor scaling over 10 process nodes. Anand holds 328 U.S. (over 800 worldwide) patents granted for pioneering work in the fabrication of CMOS and HBT transistors based on Si, SiGe, Ge and III-V compound semiconductor materials. Anand graduated from University of Southern California with Ph.D. in Materials Science and Engineering in 1993.