BIOGRAPHY
Dr. Victor Moroz is a Synopsys Fellow, engaged in a variety of projects on modeling Design-Technology Co-Optimization, FinFETs, gate-all-around transistors, stress engineering, 3D ICs, transistor scaling, cryogenic devices, Middle-Of-Line and Back-End-Of-Line resistance and capacitance, solar cell design, innovative patterning, random and systematic variability, junction leakage, non-Si transistors, and atomistic effects in layer growth and doping. Several facets of this activity are reflected in three book chapters, a 100+ technical papers and over 300 US and international patents. Victor has been involved in technical committees at ITRS, IEDM, SISPAD, DFM&Y, ECS, IRPS, EDTM, and ESSDERC, including serving as a Technical Chair of SISPAD 2018 and is currently serving as an Editor of IEEE Electron Device Letters.