Powering the Future of AI: Architecting for Scalable, Energy-Efficient Compute
Demand for high performance AI compute is growing exponentially, but power isn’t keeping up. As energy efficiency is shown to be a limiter for AI growth, this talk outlines how AMD is advancing compute architecture through chiplet architecture, advanced packaging, and memory-compute locality. We’ll explore innovations that reduce energy per operation from 3.5D stacking and hybrid bonding to integrated power delivery and co-packaged optics. Mark Fuselier will show that the path to scalable AI is shifting from maximizing raw performance to maximizing performance per watt—and how AMD is leading this transition by enabling energy-efficient AI at scale.
BIOGRAPHY
Mark Fuselier is senior vice president of Technology and Product Engineering at AMD. He is responsible for silicon and packaging technology development and new product introduction engineering.
Fuselier has more than 29 years of semiconductor industry experience and has been involved in the development and production of process technology generations spanning from .35 micron through 2nm across multiple fabs and product families. He played a central role in the development and productization of computing solutions such as 2nm, multi-core CPU and GPU SoC integration, heterogenous APUs, 2.5D and 3D chip-packaging, and chiplet System in Package (SiP) integration.
Fuselier holds a Master of Science degree in electrical engineering and Master of Business Administration from the University of Texas at Austin. He is a member of IEEE and the Electron Devices Society