Emerging Trends in Advanced Packaging of Semiconductors
ABSTRACT
With the insatiable demand to build high performance processors for the data center, advanced packaging is playing a central role in enabling the products. The talk will discuss the trends in compute performance, power efficiency, memory and IO access as it relates to silicon chiplets and heterogeneous 3D and 2.5D physical integration schemes. The need to develop material and equipment for interconnect technologies as well as developing a standards based ecosystem for chiplet based integration will be highlighted
BIOGRAPHY
Ram S. Viswanath is the Vice President and Director of Architecture and Pathfinding in the Technology Development organization at Intel. He leads a team responsible for introducing innovative packaging technologies for client, server, and graphics processors.
His focus recently has been on optimizing inter-die interconnect technologies to enable heterogeneous integration of XPUs on the package. Under Viswanath’s leadership, the silicon and package technologies have been carefully co-engineered with products to optimize for cost and performance.
Viswanath holds a Ph.D. in mechanical and aerospace engineering and is an executive member of the International Electronics Manufacturing Initiative’s technical committee.