Extreme Heterogeneity: 3D Package Opportunities & Challenges
BIOGRAPHY
Johanna M. Swan is an Intel Fellow and the Director of Package Research and Systems Solutions in Components Research within Technology Development at Intel Corporation. She leads a multidisciplinary team of researchers charged with developing novel technologies and package architectures to enable continued semiconductor scaling, mm-wave communications at various length scales and differentiating capabilities within packaging.
An expert in advanced electronic packaging technologies, Swan began her Intel career in 2000, focusing initially on packaging solutions for wireless, cellular and memory products. She initiated Intel's first through silicon via (TSV) die stacking program and led research in early TSV architectures. She and her team also developed a stacked-package chip-scale package (CSP) and a mixed-technology CSP. Since assuming her current role in 2006, Swan and her team have pioneered numerous innovative packaging technologies, including a multi-die interconnect silicon bridge and an associated enabling printing solution (EMIB) as well as more recent technologies such as Foveros Omni (ODI). She holds over 150 patents primarily in the field of electronic packaging. Before joining Intel, Swan spent 16 years at Lawrence Livermore National Lab (LLNL) as a Mechanical Engineer.