downloadGroupGroupnoun_press release_995423_000000 copyGroupnoun_Feed_96767_000000Group 19noun_pictures_1817522_000000Group 19Group 19noun_Photo_2085192_000000 Copynoun_presentation_2096081_000000Group 19Group Copy 7noun_webinar_692730_000000Path
Skip to main content

June 9, 2021

ESDA Work From Home

Join us for the first part of the Work From Home Series co-hosted by ESD Alliance and Accellera! Hear a panel of verification engineers outline a set of best practices for chip design engineers as they continue to work from home, begin planning a return to the office and determine how that might be different. 

Time

9:00 am - 10:00 am

Add to Calendar 2021-06-09 09:00:00 2021-06-09 10:00:00 ESD Alliance & Accellera - Remote Work, Remote Chip Design: Building Chips During a Pandemic Join us for the first part of the Work From Home Series co-hosted by ESD Alliance and Accellera! Hear a panel of verification engineers outline a set of best practices for chip design engineers as they continue to work from home, begin planning a return to the office and determine how that might be different.  Online, Pacific Time, United States SEMI.org contact@semi.org America/Los_Angeles public
Location

Online, Pacific Time,
United States

ESDA Work From Home

Remote Work, Remote Chip Design: Building Chips During a Pandemic

Co-Hosted by         SEMI ESD Alliance          and           Accellera Logo

The work from home dynamic created upheaval in all walks of life. This is particularly acute scenario in the semiconductor industry that experience unique challenges as engineers attempt complex chip innovation from their home offices. 

Chip design-verification engineers, accustomed to a range of robust software and hardware resources readily available within their physical office environment, are faced with new limitations. Their complicated and well-choreographed verification flows and project cycles may have taken a hit given VPN tool and system access, Zoom-based team collaboration, and necessary deep thinking interrupted with everyday home activities. 

Nonetheless, verification hasn't stopped through the pandemic and its obstacles, as verification experts will discuss during a co-sponsored panel from Accellera and the Electronic System Design (ESD) Alliance, a SEMI Technology Community. They will outline a set of best practices for chip design verification engineers as they continue to work from home, begin planning a return to the office and determine how that might be different. 

Moderator Tom Fitzpatrick from Siemens EDA will explore the range of challenges and triumphs with a panel of verification engineers from a varied range of semiconductor disciplines and company sizes. The discussion will include modifications to development practices, coping with innovations requiring intense team collaboration, the ability to evaluate and implement new methodologies, dealing with necessary visits to office labs, and the impact on product schedules. 

The virtual format will include time for audience questions. 

A follow-up panel in July featuring semiconductor executives will debate whether working from home has greater benefits than drawbacks and whether the pandemic produced a paradigm shift and permanently altered office culture. Part of the discussion will explore how they are preparing for an orderly transition back to the office.

Featured Speakers

Moderator
Tom Fitzpatrick
Strategic Verification Architect, Siemens EDA
Dr. Ashish Darbari
CEO, Axiomise
Mark Glasser
Member of the Technical Staff, Cerebras
Martin Barnasconi
Technical Director System Design & Verification Methodologies, NXP
Lu Dai
Senior Director of Engineering, Qualcomm

Registration

Free registration sponsored by ESD Alliance and Accellera.

Paul Cohen
Senior Manager, ESDA
pcohen@semi.org