Yield Enhancement / Yield Methodologies 3
Session Chairs: Victor Chan, Zhixing Li
Yield improvement in volume manufacturing requires eliminating defects and resolving parametric variations. In this session authors will be discussing methods of mitigating threshold voltage variations in SOI technologies, optimization of FINFET RIE processes to improve yield and gate leakage reduction techniques in a NOR memory process.
Thursday, May 4, 2023
8:00 AM ET
12.1 Threshold Voltage Variation due to Tailing Effect in SOI Thin Film
Joseph Ke, Priefert Dirk, Soon Huat Niew, Infineon Technologies
8:25
12.2 FIN Reveal RIE Process Optimization to Improve Device Performance and Yield
Chun Pui Kwan, Hongliang Shen, Edward Reis, Cassidy Dineen, Lillian LI, Tu Nguyen, Yevgeny Lifshitz, Robert Brown, James Chen, Lan Yang, Xiaoli He, Globalfoundries
8:50
12.3 Control Gate Device Leakage Reduction by Improving Poly Etch Uniformity and Active Area Recess
Jeff J Ye, Meng-yin Wu, Hank Liu, Micron Technology