Yield Enhancement / Yield Methodologies 2
Session Chairs: Jeff Ye, Shiv Mishra
Yield improvement is one of the primary goals in any manufacturing. This requires not only eliminating defects, but also resolving parametric detractors, addressing design marginality and systematic problems. In this session authors will be discussing yield issues, detection techniques and mitigation actions in SiC, DRAM, FINFET and PCM technologies.
Wednesday, May 3, 2023
2:35 PM ET
11.1 Silicon Carbide wafers yield enhancement with SEMVision® G3MAXFIB application at STMicroelectronics production line
Antonio Rossitto, Annalisa Cannizzaro, Antonella Di Salvo, STMicroelectronics; Massimo Battista, Daniel Harel, Antonio Laudani, Andrei MIller, Haim Pearl, Dario Nicolosi, Applied Materials
3:00
11.2 Gate and Contact Induced Drain Leakage at High Voltage Operation in DRAM
Ketaki Sarkar, John Lee, William Simpson, Bryan Orf, Laura Treider, David MacMahon, Michael Hurt, Micron Technology
3:25
11.3 Reducing Merged Silicon-Germainum (SiGe) Epitaxial Growth in FinFETs to Avoid Yield Loss
Hongying Peng, Yao Yao, Kazy Shariar, James Chen, Dylan Mafrici, Kyle Briggs, GlobalFoundries
3:55
11.4 Process Challenge in Analog Computing Hardware using Phase Change Memory (PCM)
Victor Chan, Injo Ok, Sam Choi, Tarl Gordon, Iqbal Saraf, Steven Mcdermott, Kevin Brew, Timothy Philip, Henry Utomo, Wei-Tsu Tseng, Mary Claire Silvestre, Ning Li, Juntao Li, James Demarest, Jin Ping Han, Arthur R. Gasasira, Ruturaj Pujari, Nicole Saulnier, Sean Teehan, Ishtiaq Ahsan, IBM Research