innovation

As the world enters a new era of deep tech innovation, fields such as AI chips, Advanced Computing, Autonomous Vehicles, Smart Manufacturing, and MedTech have become strategic priorities for global investors and corporate venture capital (CVC). This momentum has accelerated collaboration between startups and the semiconductor supply chain, transforming innovative ideas into scalable market solutions.As part of its effort to foster global startup engagement, SEMI connects global innovators through two key platforms — the Silicon Startups Zone and the IC Taiwan Grand Challenge (ICTGC) — to accelerate innovation across the semiconductor ecosystem.Silicon Startups Zone: A Global Stage for Semiconductor Innovation The Silicon Startups Zone serves as a gateway for global startups and investors exploring opportunities in semiconductor innovation. Launched at SEMICON Taiwan 2025, the Silicon Startups Zone is organized by SEMI with support from the National Science and Technology Council (NSTC). It features over 20 startup teams from Taiwan and around the world, showcasing advancements in AI chips, advanced packaging, EDA tools, and sustainable solutions.Through UPNext Stage presentations and live technology showcases, startups engage directly with investors, chip designers, and technology providers. SEMICON Taiwan attracts over 100,000 industry professionals, fostering new partnerships, investment discussions, and collaborations — reinforcing Taiwan’s pivotal role in connecting global innovation with the semiconductor supply chain. The Silicon Startups Zone is more than just an exhibit space — it is a starting point for collaboration and commercialization. By leveraging SEMI’s global network and Taiwan’s world-class manufacturing ecosystem, the platform accelerates startup growth and builds a sustainable pathway for next-generation innovation.The 2026 Silicon Startups Zone welcomes qualified startups to participate, offering a dedicated showcase area, UPNext Stage speaking opportunities, and exclusive marketing and media exposure. For more details, please contact Sophie Chen at [email protected] Taiwan Grand Challenge (ICTGC): Precision Scouting for Global Deep Tech Collaboration Organized by the NSTC and promoted by SEMI, the IC Taiwan Grand Challenge (ICTGC) is a global competition focused on Deep Tech innovation — based in Taiwan and open to the world. With the theme “Prototyping to Production,” ICTGC identifies startups and innovators in five key areas: AI Chip Technology, Smart Mobility, Smart Manufacturing, MedTech, and Green Technology. The program invites global startups, research institutions, and entrepreneurial teams to apply. Selected winners receive up to US $30,000 in prize funding, along with technical mentorship and access to semiconductor manufacturing resources, including EDA tools, wafer fabrication, and packaging technologies. The 2026 Call for Proposals are open now through February 28, 2026. More than a competition, ICTGC serves as a platform for collaboration — connecting the semiconductor supply chain, academia, and venture partners to help startups accelerate development and market entry. For more details on the call proposals, please contact Sophie Chen at [email protected] or submit via the Google form.Two Platforms, One Mission: Connecting Innovation for the Future Together, the Silicon Startups Zone and IC Taiwan Grand Challenge (ICTGC) create a pathway for Deep Tech startups — from discovery to collaboration and growth. Through these initiatives, SEMI connects global innovators with the semiconductor ecosystem, driving cross-border partnerships and accelerating next-generation technologies. Please click here for more information.SEMI Contact Sophie Chen, Coordinator, Technical Projects Email: [email protected]

New pilot lines offer European innovators access to the most advanced semiconductor technologies for product development and validation.The global semiconductor landscape has undergone significant transformation in recent years. With disruptions such as the semiconductor supply chain crisis and the challenges it posed to the automotive sector, Europe’s dependence on external fabrication facilities, particularly in Taiwan, has become a pressing concern. In response, the European Union (EU) introduced the EU Chips Act, a comprehensive framework designed to reduce this reliance and boost Europe’s share of the global semiconductor market. ITF Chip into the Future, hosted by imec at SEMICON Europa 2024, was a pivotal event that brought together industry leaders, policymakers, and experts to explore the implementation of the EU Chips Act and the future of Europe’s semiconductor ecosystem. Jari Kinaret, Executive Director of the Chips Joint Undertaking (Chips JU)—the body overseeing the EU’s semiconductor investments—explained, “The Chips JU is about capacity building to drive semiconductor innovation in Europe. We will continue to be dependent on the rest of the world, but we want to make sure that the rest of the world depends on us as well.” Jari Kinaret, Executive Director, Chips JUEuropean research is driving progress towards sub-nanometer fabricationOne of the pilot lines, located at imec’s research center in Belgium, is focused on advancing methods that push Moore’s Law forward by achieving smaller and more efficient circuit features. As Luc Van den hove, President and CEO of imec, explained, “imec is now powering innovation for tomorrow’s chip designs, including stacked layers of chips, with each layer containing specific functionality implemented on chip processes optimized for each function. This allows us to scale much further than if all functionality had to be implemented on a single monolithic layer.”Luc Van den hove, President and CEO, imec Another pilot line, based in France and operated by CEA-Leti, is focused on pushing the limits of technology across multiple dimensions. CEA-Leti CEO, Sébastien Dauvé, explained that the goal of the FAMES pilot line is to advance “not only FD-SOI at 10nm and 7nm nodes, but also novel non-volatile memory technologies, RF components, 3D integration, and the development of small inductors for DC-DC converters.” Sébastien Dauvé, CEO, CEA-LetiAdvancements in 3D integration and chiplet technologies are closely tied to innovation in chip packaging. Christoph Kutter, Executive Director of Fraunhofer EMS, described how the Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems (APECS) pilot line in Germany is designed to meet the needs of industrial customers’ growing demand for advanced packaging solutions. Kutter noted “Customers told us that they needed to integrate logic and power, sensors and logic, and other combinations of functions. We have built the APECS pilot line to provide what they asked for.”Christoph Kutter, Executive Director, Fraunhofer EMSThe EU Chips Act is spurring investments not only in chip fabrication but also in the underlying technologies which support chipmaking. Emmanuel Sabonnadière, EVP at Soitec, highlighted how fabrication of advanced silicon carbide (SiC) power devices “is enabled by SmartSiC™ technology from Soitec – part of a built-in-Europe solution for silicon carbide.” Sabonnadière explained that SmartSiC technology “creates very thin layers of SiC material which make really differentiated substrates supporting the production of high-performance SiC devices.” Emmanuel Sabonnadière, EVP, SoitecInnovation in materials emerged as an important theme at ITF Chip into the Future. Julien Arcamone, Vice President of Corporate R D at ASM, described the critical role of materials for atomic layer deposition (ALD) in the advancing 3D semiconductor integration. Arcamone emphasized the importance of collaboration across the semiconductor value chain, describing ASM’s partnership with imec as part of “a win-win ecosystem.” Julien Arcamone, Vice President of Corporate R D, ASMDeveloping the skills to implement advanced semiconductor technologiesWhile the EU Chips Act is subsidizing the construction of new facilities including pilot lines needed for the hardware of the semiconductor industry’s expansion – the ITF speakers underlined the equally important “software” element of the semiconductor industry ecosystem: the knowledge and expertise of the people working in the industry. One of the biggest challenges in implementing the EU Chips Act is addressing Europe’s talent gap. Katrien Marent, Executive Vice President and Chief Marketing and Communications Officer at imec, said that the gap is in part “because students who graduate in STEM subjects are not trained in advanced semiconductor technologies.” From left to right: Katrien Marent, Executive Vice President and Chief Marketing and Communications Officer, imec; Julien Arcamone, Vice President of Corporate R D, ASM; Thomas Heurung, CEO, Siemens EDA; Frédérique Le Grevès, President STMicroelectronics France and Executive Vice President, Europe France Public Affairs, STMicroelectronics; Romano Hoofman, Director imec.IC-link, imec; and Christophe Frey, Vice-President of EU engagements Managing Director, ARM.Thomas Heurung, CEO of Siemens EDA, highlighted the need for educational reform in the electronics industry. He suggested that “we might not have the right degree-level curriculum for changing times in the electronics industry. We need to change the way that we train students at university, and we need more scope for early or mid-career training on specialist micro-curriculums aimed at a particular skill or knowledge set.”The industry also struggles to attract individuals. Frédérique Le Grevès, President of STMicroelectronics France and Executive Vice President, Europe France Public Affairs of STMicroelectronics, emphasizes the importance of rebranding the industry to attract new talent. She remarked, “The word ‘semiconductor’ itself isn't very exciting—it’s even off-putting to some. By simply changing the name of educational programs, we’ve seen significant increases in enrollment. This demonstrates the power of language in shaping perceptions and interest.”Thomas Heurung of Siemens EDA also called for a stronger emphasis on entrepreneurship, noting “there is a big contrast between Europe and the US, particularly Silicon Valley.” He explained how his company’s Cre8Ventures unit had been set up to help start-ups through the key stages of creating a successful new company, including product development, attracting funding, and bringing the product to market. Thomas Fleischmann, Program Manager at Robert Bosch, explained how the EU Chips Act has accelerated the formation of the European Semiconductor Manufacturing Company (ESMC) joint venture, in which Bosch is a key stakeholder. ESMC is building a new semiconductor fabrication plant in Dresden, dedicated to producing chips for the automotive and industrial sectors. Fleischmann emphasized that ESMC will play a crucial role in helping Europe “scale advanced technologies to high volumes at a competitive cost.”In addition, the EU Chips Act also provides a broader platform for the expansion of Europe’s deep tech capacity. This includes the creation of five pilot lines, which will offer European companies access to manufacturing capacity for prototyping at the most advanced semiconductor technology nodes.Thomas Fleischmann, Program Manager, Robert BoschITF Chip into the Future at SEMICON Europa 2024 highlighted the broad scope of the EU Chips Act – not only supporting the building of advanced fabs but also providing the foundations for technology development, production, and marketing – all aimed at supporting semiconductor innovation in Europe. SEMI ContactMaria Daniela Perez, Communications ManagerEmail: [email protected]

Leaders in the semiconductor industry are finding ways to balance rapid demand growth with strategies to mitigate the risks of geopolitical uncertainty and a complex supply chain.At the CxO Summit during SEMICON Europa, industry leaders gathered to share insights into the immense opportunities ahead for the semiconductor sector, as well as the challenges that could impede growth. Laith Altimime, President of SEMI Europe, highlighted how discussions last year centered on reaching $1 trillion in global sales by 2030. “The conversation today is about how far above $1 trillion we will be in 2030,” said Altimime. “Artificial intelligence is an amazing and exciting technology, and the semiconductor industry is at the heart of it.”Laith Altimime, President, SEMI EuropeAjit Manocha, President and CEO of SEMI, described the current state of the semiconductor industry with one word – “unprecedented.” Emphasizing quantum computing as the next growth driver after AI, Manocha urged leaders to prepare for the next landmark - $4 trillion in global sales by 2040. However, the challenges facing the industry are equally unprecedented. Manocha identified four key obstacles: geopolitical volatility, the Net Zero challenge, the competition for top talent, and supply chain disruptions. “We need to work together to solve these challenges – we need unprecedented collaboration,” he explained. Ajit Manocha, President and CEO, SEMIA European Perspective on the Industry’s ChallengesWith the CHIPS Act in the US and the European Union (EU) Chips Act, the industry is also seeing unprecedented governmental engagement. Gustav Kolbe, Acting Director of Enabling and Emerging Technologies at Directorate-General for Communications Networks, Content and Technology of the European Commission, explained that Europe had been deeply impacted by the effect of trade tensions and supply chain disruptions. “In the field of semiconductors, we realized that we cannot keep doing business as usual and expect to achieve more resilience and reduced dependence on non-European supply chains,” Kolbe said. Gustav Kolbe, Acting Director of Enabling and Emerging Technologies, DG CONNECT, European CommissionJari Kinaret, Executive Director of the Chips Joint Undertaking (Chips JU), which is responsible for implementing EU Chips Act programs, described how its projects amplify the effect of EU funding by leveraging matching contributions from member states and participating companies. “This means that our budget of €4 billion actually produces investments in the semiconductor industry of about €11 billion,” he noted. Jari Kinaret, Executive Director, Chips JUThe Chips JU funded projects are designed to position Europe at the forefront of advanced semiconductor technology. Belgium’s imec, for example, is operating a Chips JU pilot line focused on leading-edge semiconductor innovation. Luc Van den hove, President and CEO of imec, highlighted the potential for 3D integration, “We can now combine multiple chips through silicon interposers with very fast connectivity between them. This allows us to build compute platforms which are far larger than what can be made with a single silicon chip,” he explained referring to this approach as “CMOS 2.0.” However, Van den hove warned that Europe cannot achieve its goals alone, emphasizing the complex semiconductor value chain and the need for collaboration. “Self-sufficiency leads to mediocrity,” he warned, advocating for a global approach that leverages the “best of the best.”Luc Van den hove, President and CEO, imecStephan Haferl, Chief Executive Officer of Comet Group, introduced the CA20, a tool designed to improve efficiency and quality in semiconductor manufacturing. The CA20 uses advanced imaging and AI to quickly identify and address production challenges, such as defects in solder bumps, without damaging components. Now fully automated, it integrates smoothly into factory workflows, providing real-time information to help manufacturers maintain high standards and increase production yields. This innovation highlights the role of new technologies in overcoming key obstacles and driving progress in the semiconductor industry.Left to right: Isabella Drolz, Vice President Marketing Product Strategy, Comet Yxlon; Laith Altimime, President, SEMI Europe; Stephan Haferl, Chief Executive Officer, Comet Group; and Dionys van de Ven, President, Comet YxlonCarlos Mazure, Chief Strategy Officer at Institute of Microelectronics – A*STAR in Singapore, illustrated this point by highlighting the institute’s focus on advanced packaging, a key Singaporean strength. “We have built a state-of-the-art 300mm prototyping line, enabling companies to implement wafer-to-wafer and chip-to-wafer bonding as well as fanout chip packaging,” Mazure said. Carlos Mazure, Chief Strategy Officer, Institute of Microelectronics – A*STARTurning back to Europe, Pierre Barnabé, CEO of Soitec, highlighted materials science as a regional strength. Soitec’s engineered substrates are driving energy efficiency breakthroughs in electronic, acoustic, and photonic applications. “We can bond anything to anything, creating advanced substrates for any active layer,” Barnabé explained. Pierre Barnabé, CEO, SoitecKai Beckmann, Member of the Executive Board and CEO Electronics at Merck KGaA, Darmstadt, Germany, also emphasized the role of materials in enabling sustainable growth. “The semiconductor industry faces a challenge with the contribution of process gases to its total greenhouse gas emissions. We hope to solve the problem by using AI to support materials research, and to design new molecules – an approach we have learned from the pharmaceuticals industry,” Beckmann shared. Kai Beckmann, Member of the Executive Board and CEO Electronics, Merck KGaA, Darmstadt, GermanyCollaboration Strengthens the Semiconductor Supply Chain Despite the breadth of enabling technologies emerging from Europe, the rapid growth in semiconductor demand has not always been matched by a secure supply. Barbara Frenkel, Member of the Executive Board Purchase at Porsche, shared that the company is collaborating with the industry to improve its access to the chips needed for automotive electrification. This includes joining industry groups such as the SEMI Global Automotive Advisory Council (GAAC) and, as she said, “learning your language.” Frenkel added, “Porsche aims to emulate Apple’s approach with Intel and Motorola to drive innovation – we will do the same with suppliers of automotive chips.”Barbara Frenkel, Member of the Executive Board Purchase, PorscheAnother solution to supply constraints is to widen the supply pipeline. John Behnke, General Manager for Smart Manufacturing at Inficon, described how smart technology can significantly improve efficiency and output. “A semiconductor fab is 100 times more complicated than anything else in the world – it is a mathematical nightmare to model it. That gives massive opportunities for improved productivity if we can implement smart control technologies,” Behnke explained. John Behnke, General Manager for Smart Manufacturing, InficonThe Challenge of Achieving Sustainable GrowthWhile the prospect of exceeding $1 trillion in annual sales energizes the industry, there is widespread recognition that growth must not come at the expense of environmental responsibility. As the industry doubles in size in the 2020s, it cannot afford to double its use of resources, such as energy or greenhouse gas emissions. Frédéric Godemel, Executive Vice President for Power Systems and Services at Schneider Electric, shared that the biggest impact on sustainability could come from “energy frugality” – using energy more efficiently. He explained that implementing data fusion in a semiconductor fab – combining detailed analysis of the operation of chillers with external data sets, such as weather conditions to allow for more efficient use – results in energy savings of 10%. “This approach saved costs, reduced CO2 emissions, and provided a financial payback in less than one year,” Godemel said.Frédéric Godemel, Executive Vice President for Power Systems and Services, Schneider ElectricThe value of smart control in fab operations was also highlighted by Katharina Westrich, Global Vice President of Electronics, Semiconductors Simulation Digital Industries at Siemens. She described how Siemens makes digital twins of factories before they are built. “This is an approach that the semiconductor industry can also adopt,” Westrich said. “A digital twin enables more efficient allocation of resources to the fab and sub-fab, allowing simulation of fab operation and optimization of processes and resources.”Katharina Westrich, Global Vice President of Electronics, Semiconductors Simulation Digital Industries, SiemensThe semiconductor industry faces a future full of opportunity, yet also marked by significant obstacles—ones that delegates at the CxO Summit are now better equipped to tackle head-on.On behalf of SEMI, the SEMI Europe team would like to express appreciation to the industry leaders for sharing their visions and readiness to collaborate during the CxO Summit.SEMI ContactCassandra Melvin, Senior Director of Business Development and OperationsEmail: [email protected]

The drive to scale nodes towards physical limits, known as "More than Moore," and the adoption of 3D architecture in chip integration strategies for advanced logic and memory applications has led to unprecedented demand for high-quality dependable materials solutions. With the aid of digital solutions, the process is expedited with higher quality and efficiency.SEMI spoke with Thorsten vom Stein, Director, Head of Process Design Semiconductor Materials at Merck KGaA, Darmstadt, Germany, about how materials innovations and advanced packaging can contribute to smarter supply chain solutions for a sustainable ecosystem.More insights into key aspects of 3D architecture in chip integration and heterogeneous integration will be shared at the Advanced Packaging Conference (APC) during SEMICON Europa 2024, Nov. 12-15 in Munich, Germany. Registration is open.SEMI: What makes the digitalization of chemical process design for semiconductor materials manufacturing so challenging at a technology level? Vom Stein: The primary challenge in digitalization of process design is achieving data rich experimentation and design flexibility from the start. When we begin the process design for a novel material solution, the freedom of design needs to be very high for optimal outcomes. For example, to identify the best sequence of unit operations to achieve best process intensification, do we need a distillation or extraction after the reaction to meet the purity requirements? At the same time, the samples from these early process trials need to have purity levels and process reliability standards for high-volume manufacturing of routine production in order to meet the requirements of our customers’ leading-edge chip integration strategies. We address this need by executing data rich experimentation starting with first trial, and thereby establish “production ready” data density in the lab.To avoid confining our design space, we therefore need highly “sensorized” and automated modular lab equipment that can give us the data density we need and flexibility at the same time.SEMI: Are data-driven approaches also applied to streamline manufacturing processes? Vom Stein: Yes, data-driven approaches are key to driving cost, quality, process reliability and sustainable excellence. As we scale up from lab experiments to high-volume manufacturing—often times increasing volumes by two or three orders of magnitude—we scale the process model virtually ahead of its physical twin to de-risk these major scale-up steps. An example of this is simulating the effect of reactor geometry on the impurity profile.Establishing this handshake between the physical asset and the process model early in the development has a lot of benefits for sustained cost efficiency of the future manufacturing process. For instance, it allows for optimization of yield and cycle times to the existing asset infrastructure. Furthermore, we can achieve quality reliability critical to our customers by establishing end-to-end correlation models that link the quality of incoming raw materials to finished good impurity profiles.Finally, we can achieve the lowest possible carbon footprint and minimize waste streams and energy intensity via process intensification by matching the unit operation sequence to the specific thermodynamics and kinetics of the process.SEMI: How can advanced packaging contribute to the pursuit of net zero? Vom Stein: Ultimately in a successful process design, we aim to achieve the maximum yield of value-added product with minimal input of resources and raw materials. So, there is an intrinsic synergy between highly intensified processes and their carbon footprint. The digitalization of process design allows us to track the CO 2 footprint during every iteration of the design. Establishing this tracking as a routine design KPI is one of the key initiatives to drive net zero semiconductor material solutions.In addition, advanced process design is a key enabler for circular value streams. We are currently working on multiple projects to recycle waste streams and re-feed them as raw materials in our processes. We are also exploring how our chemical process technology can aid our customers’ recycling efforts such as reusing lithography cleaning solvent waste streams.SEMI: In your previous talks, you emphasized the importance of diversity, equity and inclusion (DE I). How is this related to the digital revolution? Vom Stein: In the not-so-distant past, my team consisted mainly of process chemists and engineers. Now, we are working with data scientists, model developers, automation experts and many more substance matter experts on our projects. This work requires an inclusive culture to maximize the impact of these diverse sets of insights and disciplines.We also must acknowledge that, in many instances, we are exploring unchartered territory that requires a “leap of faith” culture trusting in digital models. Imagine, for example, a production plant director who is used to a stepwise physical scale-up, now being onboard with skipping physical scale-up steps by using predictive process models. It takes time to really establish a trust in the “power of data.” This type of culture is championed at Merck KGaA, Darmstadt, Germany on all levels: from CEO to the production operator. Our DE I Report showcases how we continuously build belonging for over 64,000 employees across the globe.SEMI: Merck KGaA, Darmstadt, Germany is a key contributor to semiconductor innovations. How important is it for Merck KGaA, Darmstadt, Germany to collaborate with other industry leaders to achieve goals in matters such as sustainability and DE I? Vom Stein: Collaboration with our customers and OEM partners is a key piece of achieving the molecular precision necessary to drive technology evolution that serves as the backbone to society. More and more, we need to link our material solution manufacturing process to the process parameters of the tools in the fab, ultimately improving the chip yield of our customers. To transition from the nanometer era to the angstrom era, we must establish these process correlations end to end along the value chain, which is why we are heavily engaged on our Athinia collaboration framework.Besides technology enablement, sustainability is the next avenue where cross value chain collaboration is a must to lower the CO 2 and energy footprint of our industry. To this end, we have started a joint program with Intel on AI-enabled sustainable semiconductor processes.The importance of industry collaboration is why I was so honored to participate at SEMICON Europa together with representatives from leading companies.SEMI: What did enjoy about SEMICON Europa 2023 that you would like to experience again in 2024? Vom Stein: I was really impressed by the SEMICON Europa 20 Under 30 recognition program launched during the show. The program honored the brightest young leaders who have demonstrated success in their careers in the microelectronics supply chain. We were very happy with the acknowledgement of one of our brightest minds at Merck KGaA, Darmstadt, Germany, Balazs Bordas, Digital Twin Implementation Lead. He has been instrumental for many of our pioneering efforts in this space.Such recognition programs are very important for our industry and can make a significant difference in the perception of the semiconductor industry and its ability to motivate and attract more talent. I personally hope to see similar programs in the years to come.Additional resources:Learn more about diversity and inclusion at Merck KGaA, Darmstadt, Germany.Learn more about Merck’s KGaA, Darmstadt, Germany modular lab automation approach.Merck KGaA, Darmstadt, Germany sponsored SEMICON Europa and SEMI Advanced Packaging Conference in 2023. Thorsten vom Stein is Director, Head of Process Design Semiconductor Materials at Merck KGaA, Darmstadt, Germany. Based in Darmstadt, Germany, he holds a PhD in Chemistry from the RWTH Aachen University and has extensive experience in Catalysis, Materials Science, Process Development and Value Chain Innovation.Serena Brischetto is Director of Marketing and Digital Engagement at SEMI Europe.

Silicon carbide (SiC), with its wide band gap and high thermal conductivity, is increasingly favored for semiconductor power applications across several fast-growing industries. Its ability to operate at higher voltages and frequencies enables significant efficiency gains, particularly in e-mobility, where SiC offers key advantages in size, weight, and speed compared to traditional silicon-based power devices.However, as promising as SiC is, the industry still faces critical challenges in scaling to meet growing demand. Key barriers include cost, reliability, and manufacturing capacity, all of which must be addressed for SiC to fully mature.SEMI spoke with Entegris Senior Director - Advanced Technology Engagements, Office of the CTO Mark Puttock, Ph.D., to discuss the challenges of scaling SiC power chip manufacturing from a material supplier’s perspective. Puttock shared insights ahead of his presentation at the Entegris session, Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain, taking place on November 14, 2024, at SEMICON Europa in Munich, Germany. Don’t miss the opportunity to engage with experts from Entegris and other industry leaders. Registration is now open. SEMI: Global megatrends like environmental crises and AI drive the necessity for SiC power semiconductors. What is the current status? Puttock: The increasing demand for efficient power electronics — fueled by global megatrends such as vehicle electrification, environmental de-carbonization, and the rise of power-hungry AI chips — drives the necessity of wide bandgap semiconductors. SiC offers advantages of weight, size, and speed over traditional silicon (Si) solutions, which are particularly vital in automotive applications 600V and above. However, SiC chip manufacturing has not reached the maturity of silicon-based processing. Greater maturity will help reduce costs, which will accelerate adoption in the market.SEMI: What are the main challenges in scaling SiC?Puttock: Challenges in scaling SiC power chip manufacturing to high volumes are not surprising. That’s because high volume producers have not been operating long enough to resolve early-stage issues. From a material perspective, SiC is more challenging to manage compared to Si. The challenges we identify include:Chemical Mechanical Planarization (CMP): SiC is nearly as hard as diamond and significantly harder than Si, making it challenging to achieve a high removal rate while maintaining both planarity and low defectivity. This step is crucial toward the end of the wafering process and before the epitaxial growth of device layers.Handling: SiC is more brittle than Si, making it more susceptible to damage or breakage.Implantation: SiC is more difficult to implant than Si, requiring higher temperatures and the use of aluminum instead of boron as a P-type implant species. Additionally, it is a significant challenge to achieve a reliable aluminum source with a long and stable lifetime.Thermal Processing for Wafer Growth and Epitaxy Processes: SiC processes run hotter than Si ( 2000° C for wafering, 1500° C for epitaxial growth), demanding resilient chamber parts to achieve good lifetimes.Sustainability: Because SiC is extremely hard, the CMP process requires significant amounts of slurry. Improving slurry recycling and wastewater management continues to be a challenge.On October 29, we will address these issues in our webinar, “Challenges in Scaling SiC Power Chip Manufacturing: A Material Supplier's Perspective” This session will provide valuable insights and considerations for advancing maturity in high-volume SiC power chip manufacturing. SEMI: Can you elaborate on the challenges associated with CMP for SiC wafers? Puttock: SiC wafers are challenging to process, requiring specialized materials and methods compared to traditional silicon. Defects in the SiC wafer crystal during non-optimized CMP processing can propagate into the device epitaxial layers. This leads to yield loss, increased electrical resistance, reduced performance, and wasted power.SiC wafers must be cut, ground, lapped, and polished to create the necessary surface properties before depositing active layers. As the demand for these devices grows, optimizing the CMP process is essential to ensure the desired surface quality and planarity required for device fabrication. For a deeper understanding of these challenges, we recommend downloading our latest white paper, “Solving CMP Challenges in High-Volume SiC Production,” which covers:Achieving maximum smoothness with high removal ratesReducing the total cost of ownership Optimizing CMP slurry and pads for the unique wafer chemistry and topology of SiC wafersSEMI: What do you mean by optimizing slurry for SiC CMP?Puttock: CMP slurry typically consists of abrasive nanoparticle powder dispersed in a chemically reactive solution. The objective is to achieve a smooth, defect-free surface (less than 1 A Ra) with a high removal rate (greater than 7 µm/m).Traditionally, achieving high removal rates and smooth surfaces required two separate slurries. This approach sometimes forced SiC wafer manufacturers to choose a defect-free surface over a faster, more efficient CMP process, depending on their fab capabilities. Today, optimization allows SiC wafer manufacturers to achieve both high polishing capacity and good final surface quality using a single slurry.Additionally, while the slurry is the most critical part of the CMP process, the pad must be compatible with the application. This ensures the desired planarity while also preventing scratches or contamination of the SiC wafer surface. Research shows that optimized thermoplastic polyurethane CMP pads outperform traditional thermoset polyurethane pads. The optimized pads minimize surface damage and enhance removal rates due to their bulk hardness.SEMI: What are the future challenges for SiC devices? Puttock: SiC devices are increasingly favored for their superior energy efficiency and reduced environmental impact. However, the SiC manufacturing process presents challenges due to its high-temperature operations, which consumes significant amounts of energy and shortens the lifespan of chamber components. To address this, improving efficiency in these processes will be crucial in the coming years.Recycling is another important challenge. For example, CMP slurries present an opportunity for water recycling and conservation. At Entegris, we are committed to this issue and are actively collaborating with key industry players to enhance material circularity and prioritize sustainability in our new product development.SEMI: How is Entegris contributing to advancements in SiC technology, and what initiatives or partnerships do you have planned for the near future? Puttock: Entegris is an active member of the SEMI Global Automotive Advisory Council (GAAC) and participates in a working group focused on SiC with key industry leaders such as Volkswagen, BMW, Porsche Consulting, onsemi, Infineon, STMicroelectronics, and others. Our engagement spans the entire semiconductor supply chain, collaborating with integrated device manufacturers and original equipment manufacturers in fabs worldwide. Additionally, we recently announced our latest long-term agreement with onsemi, which underscores our commitment to advancing SiC technology.SEMI: What are your expectations regarding your participation at SEMICON Europa? Puttock: SEMICON Europa is a unique platform to connect with the semiconductor and automotive ecosystems. Last year, we organized a highly successful SiC session in collaboration with SEMI at both SEMICON West and SEMICON Europa, focusing on “Connecting the Automotive Ecosystem Towards More Mature SiC Manufacturing.”This year, we will continue the discussion with industry leaders during our session, “Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain.” Our goal is to provide insights and propose solutions that will enable SiC power chips to achieve their anticipated role in future technology ecosystems.We will present alongside Porsche Consulting, and the talks will be followed by a panel discussion that will explore the current state and future prospects of SiC technology in power electronics. We invite visitors to join us at the Executive Forum on Thursday, November 14, from 1:40 – 3:00 p.m. and to visit us at Silicon Saxony booth 219 in Hall C1.About Mark PuttockMark Puttock, Ph.D., is the senior director of advanced technology engagements in the office of the CTO at Entegris. He has worked in the semiconductor industry for over 30 years with a background in physics and plasma processing. As a team member of the Entegris CTO office since 2014, Mark has followed technology trends and collaborated with Entegris’ global product development teams to develop timely and differentiated new materials, chemistries, and components for all the world’s semiconductor manufacturers. Maria Daniela Perez is Communications Manager at SEMI Europe.