Co-Packaged Optics (CPO) at Scale: Silicon Photonics, Automation, and Standards for the AI Era – an interview with Vikas Gupta, Senior Fellow, Silicon Photonics business at GlobalFoundries
AI and cloud workloads push electrical interconnects to their limits, the industry is re-architecting how light meets silicon. In our interview with Vikas Gupta, senior fellow, silicon photonics business at GlobalFoundries (GF), he explained how detachable fibers, wafer-level photonics, and new MSAs are laying the groundwork for high-volume co-packaged optics.
Why co-packaged optics now?
Data center architectures are straining under escalating bandwidth demands and power limits, especially with the rise of generative AI and dense GPU clusters. Copper traces on PCBs can still move data at high rates, but doing so requires higher signal amplitudes, complex equalization, pre-emphasis, and forward error correction—with significant power penalties. Co-packaged optics address this by moving the optical interface much closer to the electrical signal source, shrinking copper reach and improving overall energy efficiency.
Beyond switch scale-out, optical interconnects now underpin large, tightly coupled GPU systems where many devices must communicate simultaneously at extreme bandwidth. Optical fibers offer a unique advantage here: multiple wavelengths can be transmitted over the same fiber using wave division multiplexing (WDM), enabling significantly more throughput than a single copper link without signal interaction between channels.
Silicon photonics in a CMOS fab
One enabler for CPO at scale is the ability to manufacture photonic integrated circuits (PICs) on existing CMOS lines. At GF’s Malta, New York facility, more than 90% of the CMOS toolset is reused for silicon photonics, with only a few dedicated modules required for specialized steps such as advanced modulators or laser integration. This reuse allows foundries to leverage mature process control, existing capital, and established high-volume practices rather than building an entirely new line.
Silicon itself is an indirect bandgap material and cannot lase efficiently, so external light sources are needed. Today, materials such as indium phosphide are typically used to generate O-band wavelengths, with epitaxial engineering tailored to produce multiple discrete wavelengths for CWDM and beyond. As the industry tries to pack more data into each fiber, these multi-wavelength laser systems become more complex and must maintain wavelength stability even as devices self-heat.
Detachable fibers and wafer-level photonics
A core manufacturing challenge for CPO is how to attach and test optics without sacrificing yield or automation. The idea of detachable fibers originally surfaced around repairability, but Vikas noted that detachability is now more about manufacturability and automation. By decoupling the fiber from the photonic IC during most of the manufacturing flow, fabs can avoid carrying fragile pigtails through multiple process steps and instead attach fibers later in a more automated way.
This approach fits naturally with wafer-level processes.
- Surface coupling via grating couplers or turning mirrors can be implemented at wafer level, enabling optical interfaces without dicing first.
- Wafer-level optical testing becomes possible, allowing early detection of bad die before expensive packaging and assembly steps.
- Surface coupling relaxes the beachfront density limits of edge coupling; instead of being constrained by die periphery, designers can use the full surface area for optical I/O.
By shifting more optical structures and tests up to the wafer level, the industry can align CPO with high-volume silicon manufacturing practices: more automation, fewer manual fiber-handling steps, and higher throughput.
Alignment, DFM, and testing for known good modules
Aligning a 125-micron fiber to a sub-micron photonic waveguide illustrates the fundamental mechanical-to-electrical challenge in CPO. Vikas outlined three families of alignment techniques.
- Active alignment remains the industry staple, especially for pluggables, using live optical power feedback to iteratively adjust fiber position until maximum coupling is reached before locking it in place.
- Passive alignment relies on semiconductor-precision mechanical features such as etched V-grooves at the die edge, which provide self-aligned seating for fibers.
- Vision-based alignment uses fiducial marks on both the photonic IC and mechanical structures; advanced systems align crosshairs to position fibers or optical components with high accuracy.
As these systems grow more sophisticated, the same vision infrastructure supports both assembly and test. Design for manufacturability (DFM) is critical too: photonic layouts often include curvilinear shapes and sparse patterns compared to Manhattanized CMOS logic, so designers must avoid issues like dishing that could “polish away” critical waveguides. Design teams also must build in tolerance to mechanical misalignment so that realistic packaging tolerances do not compromise optical performance.
Testing strategy is another key lever for yield and cost. To support known good die and known good modules, GlobalFoundries is pushing tests upstream and inserting multiple test points throughout the optical engine build. As the bill of materials accumulates—from PICs to electrical ICs to fibers and full modules—early testing allows fabs to weed out bad die before adding more cost. Final stage tests still need to run the complete engine at speed and perform compliance checks, but earlier stages reduce the probability of expensive late-stage failures.
Thermal management in the age of liquid-cooled CPO
By definition, co-packaged optics places the optical engine next to high-power ASICs or GPUs, exposing sensitive photonic components to intense thermal environments. GPUs and switches rely increasingly on advanced air and liquid cooling, and CPO engines benefit from the same infrastructure, but they still sit near a dominant heat source.
Historically, lasers have been kept off-die for CPO because many III–V materials do not behave well at high temperatures. At the same time, the desire for greater integration is pushing industry to bring these light sources, such as InP–based lasers and optical amplifiers, closer to or onto the silicon die. This tension is driving significant reliability and packaging research to ensure long-term stability under high-temperature operation.
Thermal considerations are now explicit in emerging standards. Vikas pointed to the latest XPO MSA (eXtra-dense Pluggable Optics Multi-Source Agreement), which incorporates liquid cooling into the package form factor itself—a clear recognition that thermal management must be engineered at the architecture level, not treated as an afterthought.
Standardization: from proprietary links to open ecosystems
CPO began in a world of proprietary, bookended systems: one vendor’s GPU talking only to the same vendor’s GPU, or a single company’s switch ASICs communicating over closed optical interfaces. This created interoperability barriers and limited ecosystem scale.
Optical Fiber Communication Conference 2026 marked a turning point, with multiple multi-source agreements (MSAs) emerging around CPO and AI optics.
- The Optical Compute Interconnect (OCI) Multi-Source Agreement, backed by companies including Broadcom, AMD, Nvidia, and OpenAI, focuses on optical signaling—establishing protocols so systems from multiple vendors can interoperate optically, even though it does not yet define the electrical side.
- The Open CPO/CPX MSA, driven largely by optical vendors, targets socketed CPO and emphasizes mechanical form factor rather than signaling.
These efforts share a common recognition: the “wild west” of proprietary CPO implementations is unsustainable if the industry wants true scale. Standardization inevitably increases competition, but it also broadens participation, enables vendor mix-and-match, and accelerates adoption by system builders who need robust, multi-sourced ecosystems. Vikas expects these initial MSAs to be the first wave of ongoing standardization that will cover signaling, packaging, and system-level requirements.
Looking ahead
Scaling CPO for AI and cloud workloads will require tight coordination across device, process, packaging, and system communities. Silicon photonics lines that reuse CMOS tooling can supply the necessary volumes, but only if design teams embrace design-for-manufacturing (DFM) and tolerance-aware layouts, and if fabs push test earlier into the flow to guarantee known good modules. Detachable fibers, wafer-level coupling and testing, and sophisticated alignment systems are all moving CPO manufacturing toward higher automation and yield.
In parallel, thermal and standardization challenges are being addressed head-on through package-level liquid cooling features and new MSAs that open the ecosystem beyond single-vendor islands. Together, these trends suggest that CPO will not remain a niche technology—rather, it is on a path to becoming a mainstream building block for the next generation of AI and data center infrastructure.
Anshu Bahadur, SEMI
