Session 1—Yield Enhancement / Yield Methodologies
Chairs: Ishtiaq Ahsan, IBM Research; Janay Camp, KLA; Gary Green, Green Technology Consulting; Dieter Rathei, D R Yield
Yield improvement in today’s fabs requires deep understanding of root cause of fails and tight process control. This session covers papers that provide details of root causes of yield fails, addresses methodologies enabling tight process control and pattern matching techniques using machine learning for accelerated yield learning.
10:05am
1.1 Simulated CWAC to Eliminate1st Wafer Effect and Improve Process Capability
Kunal Raghuwansi, John LeClair, Dmitry Zhernokletov, Samsung Austin Semiconductor
10:30am
1.2 Middle of Line (MOL) Process Investigation in Ring Oscillator Failure
Victor Chan, M. Bergendahl, S. Choi, A. Gaul, J. Strane, A. Greene, J. Demarest, J. Li, L. Jiang, C. Le, S. Teehan, D Gao, IBM Research
10:55am
1.3 Characterization of Doped Oxide Films PSG/BPSG/FSG via DSIMS in Order to Eliminate Nonzero Kilometer Failures from Semiconductors Used in Automotive Industry
Thanas Budri, Jeffrey Klatt, Texas Instruments
11:20am
1.4 Qualifying Inline Xe Plasma FIB - Returning Milled Wafers Back to Production
Franz Niedermeier, Infineon; Haim Pearl, Applied Materials
11:45am
1.5 Middle of Line: Challenges and its Resolution for FinFET Technology
Shiv Kumar Mishra, Erik Geiss, Aditya Kumar, Arkadiusz Malinowsk, Kaushikee Mishra, Gao Wen Zhi, Wenhe Lin, Bangun Indajang, Dustin Slisher, GLOBALFOUNDRIES
12:15pm
Networking Lunch