3D TSV and Novel Advanced Silicon Processing
Session Chairs: Eric Eisenbraun, Rob Pearson, Marc Bergendahl
In this session we will explore novel advanced processing for FinFET performance improvements and for Quantum Devices. This session also reviews enabling process technologies for advanced 3D TSV applications like Backside Power Distribution Networks.
Wednesday, May 15, 2024
1:30PM ET
14.1 12LP FinFET CMOS Ultra-Low Leakage SRAM Devices with 0.54pa/Cell Istby
Y. Du, V. Vulcano, Y. Yao, H. Yu, W. Ma, O. Hu, GlobalFoundries
14.2 DTCO Guided Process Integration: Case Studies from FEOL & BEOL with BSPDN
M. Abedin, S. Khan, N. Lanzillo, D. Dechene, IBM Research
14.3 Q-Time Assessment on Electroplated Nickel/Gold Interface Quality
S. Paul, B. Hedrick, A. Abdel-Aziz, J. Garant, B. Yatzor, C. Schroiff, Q. Yuan, GlobalFoundries
14.4 Enabling 300 mm Wafer-Scale Fabrication of Superconducting Quantum Devices
E. Bhatia, N. Pieniazek, J. Nalaskowski, J. Mucci, W. Collison, B. Martinick, S. Olson, P. Hung, I. Wells, S. Schujman, C. Johnson, T. Murray, S. Papa Rao, NY CREATES; H. Frost, University at Albany (SUNY)