450mm Update on SEMI Standards

450mm Update on SEMI Standards

SEMI Standards task forces are working on encouraging the industry to collaborate on key issues like the technical parameters for 450mm silicon wafers, physical interfaces, carriers, assembly and packaging. To date, SEMI has 13 task forces working on 450mm and has published fourteen (14) 450mm standards with 10 more in the pipeline.

Here’s an update on the newly-published SEMI 450mm specifications as well as the other 450mm SEMI Standards.

 
450mm Polished Single Crystal Silicon Wafer Specification

SEMI M1-0413 – The Specification for Polished Single Crystal Silicon Wafers was revised and published in April 2013. The new edition includes a significant addition of a 450mm polished single crystal polished wafer specification and the guide for specifying 450 mm wafer for 32, 22, and 16 nm technology generation.  Today, the specification requirements for 450mm diameter wafers are much more extensive that those of previous smaller diameters. Standardized parameters include edge profile, warp, conductivity, dopant, and surface conditions.

To provide some context about history, SEMI M1 was originally published in 1980s. The first wafer specification was 50mm (2 inch) or about the width of credit card.   Over the years, wafers got larger and larger.  In the early 1990s, the wafer size was increased to 200mm (8 inch), and in 1997, the 300mm (12 inch) wafer was standardized. A 300mm wafer may yield 2.25 times more chips per wafer than an older 200mm wafer.  For 450mm, 5 times more chips per wafer can be squeezed out of a wafer compared to that of 200mm wafer, yet the process of making the chip takes about the same amount of time to go through the factory.  More chips are produced per wafer, which in turns reduces the cost.  Thus wafer manufacturers and users are moving ahead to formalize a specification for 45 mm wafer.  The International Polished Wafer Task Force will continue to refine associated parameters to adapt to the dynamic semiconductor industry.

More information: www.semi.org/node/41061
Wafer Specification Standard
  • SEMI M1-0413, Specification for Polished Single Crystal Silicon Wafers

SEMI M1 provides the essential dimensional and certain other common characteristics of silicon wafers, including polished wafers as well as substrates for epitaxial and certain other kinds of silicon wafers.

FOSB Standards
  • SEMI M80-0812, Mechanical Specification for Front-Opening Shipping Box Used to Transport and Ship 450 mm Wafers
  • SEMI E162-0912, Mechanical Interface Specification for 450 mm Front-Opening Shipping Box Load Port

SEMI M80 specifies the FOSB used to ship 450mm wafers from wafer suppliers to their customers (typically IC manufacturers), while maintaining wafer quality. SEMI E162 defines the basic interface dimensions of a load port on the semiconductor manufacturing equipment, where 450 FOSB can be loaded and unloaded. The intention of SEMI E162 is to define a set of requirement and features to enable interoperability of load ports and carriers without limiting innovative solutions.

Assembly and Packaging Standard

These Standards specify mechanical features for the 450mm wafer tape frame and cassette used between the wafer mounting process and the die-bonding process. The Assembly and Packaging Committee is now developing Standard for the load port interface between the frame cassette and processing equipment (Document 4965C, New Standard for Mechanical Interface Specification for 450 mm Load Port for Tape Frame Cassettes in the Backend Process).

Guide to SEMI Standard for 450mm Wafers (Auxiliary Information)

The image below shows where 450mm standards development is taking place.

For more information

All of the published standards in this article are available in SEMIViews. Individual standards can be purchased from the SEMI Web store using the links below.

  • SEMI M1-0413, Specifications for Polished Single Crystal Silicon Wafers
  • SEMI M49-0912, Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 22 nm Technology Generations
  • SEMI M52-0912, Guide for Specifying Scanning Surface Inspection Systems for Silicon Wafers for the 130 nm to 11 nm Technology Generations
  • SEMI M62-0413, Specification for Silicon Epitaxial Wafers
  • SEMI M74-1108 (Reapproved 0413), Specification for 450 mm Diameter Mechanical Handling Polished Wafer
  • SEMI M76-0710, Specification for Developmental 450 mm Diameter Polished Single Crystal Wafer
  • SEMI M80-0812, Mechanical Specification for Front-Opening Shipping Box Used to Transport and Ship 450 mm Wafers
  • SEMI E154-0612, Mechanical Interface for 450 mm Load Port
  • SEMI E156-0710, Mechanical Specification for 450 mm AMHS Stocker to Transport Interface
  • SEMI E158-0912, Mechanical Specification for Fab Wafer Carrier Used to Transport and Store 450mm Wafers (450 FOUP) and Kinematic Coupling
  • SEMI E159-0912, Mechanical Specification for Multi-Application Carrier (MAC) Used to Transport and Ship 450 mm Wafers
  • SEMI E162-0912, Mechanical Interface Specification for 450 mm Front-Opening Shipping Box Load Port
  • SEMI G88-0211, Specification for Tape Frame for 450 mm Wafer
  • SEMI G92-0412, Specification for Tape Frame Cassette for 450 mm Wafer

For additional information on draft documents under development, see the Standards New Activity Report Forms (SNARFs) linked below.

  • Doc. 4812, Guide for Flatness Measurement on 450 mm Wafers
  • Doc. 4965C, Mechanical Interface Specification for 450 mm Load Port for Tape Frame Cassettes in the Backend Process
  • Doc. 5069, Specification for 450 mm Wafer Shipping System
  • Doc. 5070A, Revision to SEMI M76-0710, Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers [Re: Wafer Edge Design]
  • Doc.5430A, Revision to SEMI M73-0309, Test Methods for Extracting Relevant Characteristics from Measured Wafer Edge Profiles (To include 450 mm wafer edge profile parameters)
  • Doc. 5071, Revision to SEMI M76-0710, Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers  [Re: Back Surface Contamination and Defect Requirements]
  • Doc. 5463, Revision to SEMI E83-1106, Specification for 300 mm PGV Mechanical Docking Flange with title change to: Specification for PGV Mechanical Docking Flange
  • Doc. 5464, Revision to SEMI E154-0612, Mechanical Interface Specification for 450 mm Load Port
  • Doc. 5488A, Specification for 450 mm Cluster Module Interface: Mechanical Interface and Transport Standard
  • Doc. 5524, Line item revisions to SEMI E156-0710, Mechanical Specification for 450 mm AMHS Stocker to Transport Interface
About the Silicon Wafer, Physical Interfaces & Carriers, and Assembly & Packaging Committees
Physical Interfaces & Carriers Committee

This committee develops specifications to enhance the manufacturing capability of the semiconductor industry, specifically addressing mechanical, electrical, and special equipment specifications; and material movement integration, including substrate support and containment structures. For more information on committee activities, please contact Michael Tran at mtran@semi.org or Hiro'fumi Kanno at hkanno@semi.org.

Silicon Wafer Committee

This committee develops international standards fulfilling the requirements for commercial silicon wafers. Silicon Wafer Committee standardization includes specifications and guides for silicon wafers, test methods for silicon wafer quality and geometry, shipping box related topics, wafer ID related topics, and business related topics to support smooth communication between silicon suppliers and customers. For more information on committee activities, please contact Kevin Nguyen at knguyen@semi.org  or Hiro’fumi Kanno at hkanno@semi.org.

Assembly & Packaging Committee

This committee develops specifications to enhance the manufacturing capability of the semiconductor industry as it relates to the packaging and assembly of the semiconductor chip, including the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration. This committee also discusses total infrastructure for Chip to Final Set system and processes such as Testing and Design Software, Transportation Tools, Reliability and Traceability issues, EHS issues, Inspection methods, etc. For more information on committee activities, please contact Paul Trio at ptrio@semi.org or Naoko Tejima at ntejima@semi.org.

 

April 24, 2013