Laith Altimime, President, SEMI Europe
Biography
Laith Altimime, as President of SEMI Europe, leads SEMI’s activities in Europe and the Middle East and Africa (EMEA). Altimime has P&L responsibility as well as ownership of all Europe region programs and events, including SEMICON Europa. He is responsible for establishing industry standards, advocacy, community development, expositions, and programs. He provides support and services to SEMI members worldwide that have supply chain interests in Europe. He manages and nurtures relationships with SEMI members in the region and globally, as well as with local associations and constituents in industry, government, and academia. Altimime has more than 30 years of international experience in the semiconductor industry. Prior to joining SEMI in 2015, He held senior leadership positions at NEC, KLA-Tencor, Infineon, Qimonda, and imec. Altimime holds an MSc from Heriot-Watt University, Scotland.
Gerald Beyer, Program Manager, imec
Biography
Giorgio Cesana, Director, Heterogeneous Integration Transformation Program, Global Technology R&D, STMicroelectronics
Abstract
While heterogeneous integration is often presented as a modern disruption, it has been a core industrial reality for over thirty years, evolving from foundational System-in-Package (SiP) solutions in sensors (both MEMS and imaging) and specialised functions to today’s advanced 3D architectures. Drawing on STMicroelectronics’ legacy, this presentation demonstrates that Europe’s technological edge is rooted in a long-standing mastery of functional diversity. The specific nature of products designed and manufactured in Europe, particularly for industrial and automotive applications, is uniquely positioned to be enhanced by the higher value and performance density that SiP provides. Modern 3D and other advanced integration techniques are now extending this legacy, enabling deeper integration and a level of circuit complexity that traditional monolithic scaling can no longer achieve. By shifting the focus toward this higher-value system integration, the European semiconductor industry can unlock new economic drivers while reinforcing its technological resilience. Mastering these sophisticated architectures is a strategic necessity for securing sovereignty across critical domains in an increasingly volatile global supply chain. Ultimately, leveraging this 30-year heritage of heterogeneous innovation is the key to defining Europe’s long-term positioning in the global semiconductor landscape.
Biography
Giorgio Cesana is Director of the Heterogeneous Integration Transformation Program within Global Technology R&D at STMicroelectronics. He has over 30 years of experience in the semiconductor industry, having joined ST in 1994 and held a variety of technical and strategic leadership roles.
Over the course of his career, Giorgio’s responsibilities have spanned EDA development, management of digital libraries, and coordination of collaborative processes and tools for the “Crolles2 Alliance”, the joint R&D program among ST, NXP and Freescale.
He subsequently managed programs for key advanced CMOS products and led the technology marketing team responsible for defining CMOS-based technology platforms, including ST’s FD-SOI technology, while monitoring emerging industry trends and providing PPA benchmark analyses. Giorgio then directed Technology Strategy, contributing to the definition of long-term technology roadmaps.
From 2014 to 2018, he also served as Executive Director of the SOI Industry Consortium.
Séverine Chéramy, Director of Advanced Heterogeneous Integration Technologies, SCINTIL Photonics
Abstract
The demand for O-band multi-wavelength (frequency) laser sources, with 8-16 lines precisely spaced by 100 GHz or 200 GHz, has grown rapidly in recent years, driven by Co-Packaged Optics (CPO) applications.
In this talk, SCINTIL Photonics will report on its single-chip DWDM laser source, fabricated from its III-V on silicon heterogeneous laser integration process leveraging standard silicon photonics. The chip monolithically integrates 8 to 16 Distributed FeedBack (DFB) lasers, their monitoring PhotoDiodes (PD), and muxes.
The packaging of the chip and its control electronics have been developed to match the OIF standardized ELSFP form factor.
Biography
Séverine Chéramy holds an engineering degree, having specialized in material science. She started her career in hardware secure solutions for contactless smart cards & electronic passports, then joined CEA-Leti in 2008, occupying various roles related to semiconductor 3D integration and advanced packaging.
In 2021, she joined ALEDIA, a spin-off of CEA-Leti, as product line manager in LED for display applications. She’s now back in heterogeneous integration as director of advanced technologies at Scintil Photonics, a Leti spin-off focused on Silicon Photonics and laser-integrated solutions.
Mohamed Elghazzali, Manager Technology Development, Evatec
Abstract
AI computing is accelerating the adoption of advanced packaging, where higher bandwidth, tighter power delivery, and larger heterogeneous modules push substrate formats beyond traditional wafers toward fan-out panel-level packaging (FOPLP) and large organic IC substrates.
A key enabler is reliable, high-throughput metallization on Glass/polymer substrates, materials that are lightweight and cost-effective, yet highly sensitive to outgassing, surface chemistry, and thermal/mechanical distortion during vacuum processing.
This session introduces Evatec's high‑volume manufacturing panel-level PVD cluster solution for large-area substrates, designed to deliver uniform metallic thin films with low resistivity and robust adhesion.
In addition, deep reactive ion etching (DRIE) of vias in PI or silica-filled organic build-up films is presented, a crucial capability to integrate into a panel-level solution.
The etch process feasibility and window definition are first established on an 8‑inch inductively coupled plasma (ICP) module, enabling rapid DOEs to optimize anisotropy, selectivity, and via profile, and to validate mask removal and landing‑pad protection.
The qualified baseline is then transferred to an automated cluster platform compatible with large-area polymer substrates. EVATEC integrated platform combines atmospheric-pressure degassing to remove volatile species prior to vacuum steps, full-face dual-frequency CCP plasma treatment for surface activation, Ar sputter etch for in-situ cleaning, Deep reactive ion etching (DRIE) for via formation and sputter deposition of RDL or BSM metallization.
EVATEC Solution is enabling scalable, ultra‑small vertical interconnects essential for bandwidth‑ and energy‑efficient AI/HPC chiplet packages.
Biography
Mohamed Elghazzali is the Technology Development and Advanced Packaging Program Manager at EVATEC AG, where he is responsible for the development and industrialization of PVD and plasma etch hardware and processes for semiconductor and advanced packaging applications. He brings over 25 years of experience in vacuum‑based thin‑film deposition, plasma processing, and equipment innovation, with a strong focus on 3D integration and heterogeneous packaging.
He holds a diploma in Materials Science from the University of Erlangen‑Nürnberg, and began his career developing advanced manufacturing processes for ceramics and fiber‑glass production. In 2000, Mohamed joined Oerlikon’s Thin Film R&D organization, where he acted as scientist and program lead for multiple innovation projects covering non‑volatile memory devices, micro‑bolometers, thin‑film heads, and fan‑out wafer‑level packaging technologies.
His technical contributions span directional sputtering, high‑ionization PVD (HiPIMS), and metallization solutions for TSV and TGV architectures, addressing step coverage, sidewall uniformity, and interface reliability challenges critical to 3D integration. He has been deeply involved in the co‑development of hardware architectures and process concepts for Semiconductor, MEMS, and Advanced Packaging manufacturing.
Since 2015, Mohamed has served as a Senior Scientist at EVATEC. From 2018 to 2023, he was a key technical leader in the FO‑PLP and IC‑Substrate programs, driving the development of panel‑level PVD coating systems for large‑area substrates, improving throughput and cost‑of‑ownership, and redesigning CCP plasma etch reactors for RIE and DRIE, enabling enhanced profile control, uniformity, and process robustness for advanced packaging and 3D integration applications.
Didier Floriot, Strategy Director, Technology, Devices and Materials, Thales Land and Air Systems – Global Business Unit
Abstract
Primidi is the project supporting the deployment of a major European OSAT based on a 300 mm fab line serving needs in advanced packaging integration. Initiated by Foxcon, Radiall and Thales and associated companies, the Joint Venture will propose up-to-date technologies based on FO-WLP supporting SiP development for advanced sensors mixing optical, digital and analogue functions and Digital SiP for AI / HPC applications. The economic model has been specifically optimised to address European industries operating from 2029.
Biography
Didier Floriot graduated from Supelec in 1992 as electrical engineering in Semiconductor Physics. He received his M.S. and PhD from the University of Paris VI in 1993 and 1995 in the domain of III-V semiconductors. He joined the Thales Research & Technology Centre and worked on the development of the power InGaP/GaAs HBT technology up to his qualification. From 2000 to 2007, he was team leader at Alcatel Thales III-V Lab, a joint research group on III-V opto-microwave devices and power semiconductors. He joined UMS (United Monolithic Semiconductors) in 2007, in charge of technological and product cooperation with a focus on wide bandgap Sc. He occupied different positions up to the Director of Technology Innovation. In 2021, he joined Thales SA as Director Corporate covering the domain of specific technologies, including advanced technology of integration. Since 2026, he has been Director of Technologies, Devices, and Materials at the Global Business Unit Land and Air Systems at Thales. He is driving the technical & industrial parts of the project of transferring advanced packaging technology (Foxconn / Thales / Radiall Joint Venture).
Tom Friedrichson, Director of Product and Program Management, Lam Research
Abstract
The rapid growth of advanced packaging is transforming how the industry thinks about capacity, scalability, and technology readiness. As architectures become more complex and volumes increase, success increasingly depends on the ability to evolve processes and equipment at the pace of market demand, without breaking continuity between development
and manufacturing.
This session explores how panel-level processing provides a scalable framework for that evolution. At Lam Research, this continuity is reflected in a panel ecosystem that spans from initial prototyping with Minicell, through pilot line learning and mid-volume manufacturing with Kallisto, to high-volume production with Phoenix, all based on consistent process and equipment principles. By connecting development, qualification, and volume of manufacturing within a consistent panel approach, the industry can reduce risk, accelerate implementation, and respond more predictably to market expansion. The discussion highlights how growing demand for advanced packaging directly drives technology development, and why aligned scaling strategies are becoming critical for future fab implementation.
Biography
Tom Friedrichson is Director of Product and Program Management at Lam Research in Salzburg, Austria, where he is responsible for defining product direction and leading the execution of advanced semiconductor and panel‑based manufacturing solutions.
Tom Friedrichson brings more than ten years of experience across the full product lifecycle, supported by a strong technical background in semiconductor process engineering, equipment industrialization, and manufacturing ramp‑ups. His career includes international assignments in Asia, where he established new cleanroom operations and electroplating process lines from equipment selection through volume production. This hands‑on experience informs his focus on scalability, reliability, and operational readiness. At Lam Research, Tom Friedrichson oversees product strategy, technology development, and program execution to guide systems from concept to production. Previously, he held the same position at Semsysco for more than seven years, managing product direction and program execution for advanced manufacturing.
Shripad Gokhale, Senior Principal Engineer- Semiconductor Packaging R&D, Intel Corporation
Abstract
Biography
Shripad Gokhale is a Senior Principal Engineer in Advanced Packaging Technology Development at Intel, where he leads early customer engagement and assembly engineering research in EMIB scaling for multi‑die, large‑form‑factor chiplet-based systems within Intel Foundry. With nearly two decades of experience, he has driven architecturally significant packaging innovations spanning heterogeneous integration (EMIB), 3D stacking (Foveros), chip–package interactions, and system‑level thermo‑mechanical and reliability co‑design. His technical leadership was critical to Intel’s first‑generation Foveros enablement and high‑yield EMIB product ramps.
Shripad is an Intel Achievement Award recipient, the author of 16 patents and 20+ technical publications, and a member of Intel’s IP committee. He holds a PhD in Chemical Engineering from Rensselaer Polytechnic Institute and currently leads iNEMI consortium projects on low‑temperature materials and large‑form‑factor packaging—bringing deep, hands‑on design and process leadership at the intersection of chiplet architecture and manufacturable 3D systems.
Volker Herbig, Vice President, BU Microsystems & Photonics, X-FAB
Abstract
Biography
Kurt Herremans, Program Director Automotive, imec
Abstract
As compute demands continue to rise across automotive, robotics, aerospace and autonomous systems, chiplets are emerging as a critical path to scalable, affordable and interoperable edge platforms. In this presentation, Kurt Herremans of imec will outline imec’s Autonomous Edge Chiplet Program journey, from its automotive chiplet foundations toward a broader cross-industry architecture for autonomous edge applications.
The talk will cover the need for open chiplet standards, the evolution from automotive-focused programs to AECP/AECF, and imec’s work on quality, reliability, packaging, architecture and reference platforms. It will also highlight recent demonstrators, including QnR and architecture emulation activities, and introduce the Reference Architecture Specification as a practical recipe for building future autonomous edge chiplet ecosystems.
Biography
Kurt Herremans is the program director of automotive at imec. Kurt is a key driver behind the imec industry call out on Automotive Chiplets and the initialisation of a pre-competitive research program on them.
Prior to joining imec, Kurt was a principal engineer at Intel, working on multiple generations of automotive SoCs and segment-specific AI accelerators. For his work on Automotive SoC designs, Kurt received the Intel Achievement Award in 2019.
Kurt Herremans holds a Master of Science degree from the University of UCLL Leuven.
Vygintas Jankus, Display Partnership Manager, CEA-Leti
Abstract
CEA is working on a massively parallel MicroLED-based optical links for point-to-point (xPU/xPU, xPU/HBM) interconnects to be used on board and in rack (up to 10 m) in HPC and data centers. They could enable, for example, pooled or shared memory / GPU architectures. Our approach combines device and circuit optimization, 3D integration such as hybrid bonding & high-density TSVs, and system modelling, enabling scalable fabrication on 200 mm and 300 mm in standard foundries. We are aiming to reach <1 pj/bit and 10.5 Tbps/mm.
Biography
Vygintas Jankus is responsible for industrial partnerships for MicroLED & OLED technologies at CEA-Leti in Grenoble. He helps partners to develop these technologies for optical & data communication, AR/VR, automotive, and other applications.
Chris Jones, Senior Director, Product Management, KLA SPTS Division
Biography
Chris Jones is Senior Director of PVD Product Management at SPTS, responsible for the SPTS PVD product line, covering all aspects of marketing including product positioning and the provision of support to the worldwide sales team.
After completing his BEng in Mechanical Engineering in 1995 at the University of Bristol, UK, he joined SPTS working in Customer Support and then Process Engineering before moving into Product Management in 2004. Chris has presented widely on SPTS products and is an author of several technical articles.
Seung Kang, SVP, Head of Semiconductor Strategy & Business Development, Adeia
Abstract
Biography
Dr. Seung Kang is Senior Vice President of Adeia and serves as Head of Semiconductor Strategy and Business Development, where he oversees strategic semiconductor programs encompassing technology, design, and system co-optimisation. Prior to joining Adeia, Dr. Kang held a globally recognised career at Qualcomm Technologies, Inc., where he spearheaded the Advanced Memory Program, pioneering early R&D and IP validation across the semiconductor ecosystem. His leadership also extended to the development of foundation logic IP for semiconductor nodes ranging from 7 nanometers to sub-3 nanometers, supporting Qualcomm's flagship mobile, automotive, AI, and IoT products. Before his tenure at Qualcomm, Dr. Kang made significant contributions at Lucent Technologies, Bell Laboratories and Lawrence Berkeley National Laboratory. He earned his B.S. and M.S. degrees from Seoul National University, Korea, and a PhD from the University of California, Berkeley. Dr. Kang is a highly accomplished inventor, holding 250 U.S. patents and over 1000 patents granted globally. His research contributions are widely recognised, with over 100 published papers. He served as a Distinguished Lecturer for the IEEE Electron Device Society from 2014 to 2018 and has been a Specially Appointed Visiting Professor at the Centre for Innovative Integrated Electronic Systems, Tohoku University, Japan.
Walter Kocon, Head of 3D Heterogeneous Integration, GlobalFoundries
Abstract
Biography
Andrej Kolbasow, Sales & Head of Low Pressure Plasma, Plasmatreat GmbH
Abstract
The increasing adoption of co-packaged optics and photonic integration is driving new requirements for surface preparation, bonding quality, contamination control, and reliability. Interfaces between optical, electronic, and packaging components must meet stringent performance criteria while supporting scalable manufacturing.
This presentation explores the role of low-pressure plasma technology in photonic packaging processes, including surface activation, organic contamination removal, adhesion promotion, and preparation of optical and semiconductor materials prior to bonding and assembly. Examples from advanced packaging and photonic device manufacturing will demonstrate how plasma-assisted surface engineering contributes to improved process consistency, enhanced interface quality, and long-term reliability in next-generation optical interconnect and co-packaged optics applications.
Biography
Andrej Kolbasow is a plasma technology specialist with a strong background in semiconductor manufacturing, advanced packaging, and surface engineering. Prior to joining Plasmatreat, he worked at Pac Tech – Packaging Technologies, where he gained extensive experience in semiconductor packaging technologies and manufacturing processes.
His current work focuses on low-pressure plasma technologies for semiconductor and photonic applications, including surface activation, contamination removal, adhesion enhancement, and process integration for advanced packaging. He is particularly engaged in the application of plasma processes for hybrid bonding, wafer-level packaging, photonic integration, and next-generation semiconductor manufacturing.
Combining expertise in plasma physics, process development, and semiconductor packaging, Andrej supports the implementation of plasma-based solutions that improve interface quality, process reliability, and manufacturing performance in advanced electronics production.
Michael Kubis, Senior Manager System Engineering ASML B.V
Abstract
Lithography resolution has been driving the dimensional scaling of semiconductor devices, but nowadays it is more and more complemented with device-level 3D architectures (such as Gate-all-around) and system-level 3D integration (such as stacked SRAM on Logic).
Hybrid wafer-to-wafer bonding is a disruptive innovation that offers array efficiency and performance gains for memory (NAND, DRAM) devices. When these bonded wafers are further processed, lithography patterning has to achieve tight scanner overlay control despite a large bonding-related distortion.
In this presentation, we will discuss the implications of the hybrid bonding process on scanner alignment, overlay metrology, and overlay control for the post-bonding exposures. We will show that a significant improvement is possible to meet the overlay performance requirements by applying high-order corrections per exposure of the scanner, and we will discuss additional opportunities to improve the performance.
Biography
Michael Kubis has been working in the area of optical lithography and process control since 2001. He received his PhD in material science and solid state physics at the University of Technology in Dresden, Germany, in 2000. He worked as a Process Engineer and Senior Manager in Deep-Trench technology DRAM R&D and HVM of Infineon and Qimonda until joining ASML, where he became a System Engineer for on-product overlay applications. Since 2016, he is Senior Manager of System Engineering teams at ASML with special emphasis on metrology, patterning control, and technology roadmaps.
Harald Kuhn, Executive Director, Fraunhofer ENAS
Abstract
Biography
Prof. Dr. Harald Kuhn has extensive experience in the semiconductor and high-tech sectors, gained in international companies. He is the Executive Director of Fraunhofer ENAS in Chemnitz, Chair of Smart Systems Integration at Chemnitz University of Technology, and Director of the Center for Micro and Nano Technologies (ZfM) within the Faculty of Electrical Engineering and Information Technology. His career includes leadership roles with a focus on microelectronics, automation, Industry 4.0, and digitalization; he has led international teams and driven innovation. His research concentrates on holistic systems, including smart systems, MEMS sensors, nanotechnologies, and system integration, with an emphasis on AI-powered production and hardware security. ENAS and ZfM develop prototypes, foster collaboration, and enhance the international visibility of Chemnitz University of Technology. His international orientation is reflected in collaborations with Asian partners in microelectronics, system integration, and AI, including MoU projects in in-memory computing and quantum communication. He views this as a bridge between Saxony, a European microelectronics hub, and Asian innovation centers, and notes that it opens opportunities for Vietnam in in-memory computing, SiC power electronics, MEMS system integration, and ASEAN knowledge transfer.
Carlos Lee, Director General, EPIC – European Photonics Industry Consortium
Abstract
Biography
Carlos Lee is Director General at EPIC, the European Photonics Industry Consortium, the largest photonics industry association in the world representing more than 800 members across 33 countries. As part of the EPIC mission, Carlos works closely with industrial photonic companies to ensure a vibrant and competitive ecosystem by maintaining a strong international network and acting as a catalyst and facilitator for technological and commercial advancement. He brings with him a strong background in semiconductors which was acquired through several management positions held at the international association SEMI. He has been responsible in Europe for the SEMI International Standards program, managed technical and executive programs, and, together with the advisory board, advocated for a more competitive semiconductor and photovoltaic manufacturing industry.
Carlos has a BBA in Finance and an MBA in Leadership & Change Management from United Business Institutes. He lives with his spouse and three children in Belgium.
Tony Maindron, Industrial Key Account Manager, CEA-Leti
Biography
Tony Maindron received his PhD in semiconductor science from INRS Energie, Matériaux et Télécommunications, in 2002, in Montréal (Canada). He used to work for Technicolor in Rennes, France, (former Thomson R&D centre in France) where he was an engineer for the development of displays incorporating OLED technology. He joined the CEA-LETI Photonics Department in 2007 where he developed thin film encapsulation, based on Atomic Layer Deposition technology, and color filter technology for OLED-based microdisplays. He moved to Minalogic, a French Innovation cluster based in Grenoble, for 3 three years between 2021 and 2024, as director of micro, nano and quantum technologies. Since 2025 he is back at CEA as an industrial partnership officer in 3D integration and advanced packaging technologies.
Joscha Malin, Director of Product Marketing for Software Solutions, Comet
Abstract
The global demand for AI, high-performance computing, IoT, and next-generation mobility is driving rapid innovation in advanced semiconductor packaging, including emerging glass panel approaches. As packaging complexity increases and feature sizes shrink, manufacturers require inspection solutions that support faster process optimization, yield improvement, and defect analysis.
This presentation will show how combining advanced 3D X-ray inspection with AI-enhanced image analysis enables scalable inspection workflows for advanced packaging applications. Using glass panel inspection as an example, it will highlight how our AI image analysis software platform helps engineers gain deeper insights from complex X-ray data, accelerate defect analysis, and expand the practical application range of non-destructive 3D X-ray inspection.
Biography
Joscha Malin is the Director of Product Marketing for Software Solutions at the Systems Division of Comet that specializes in supplying X-ray and CT inspection solutions with a particular focus on the Semiconductor R&D and production sectors. In his role, Joscha oversees the division's software product portfolio, with the goal to enhance customer productivity by automation and empower them by data-driven insights derived from X-ray and CT image data. Joscha started his career with an Engineering diploma in Microelectronics from the Technical University Hamburg-Harburg. Over the years, he has worked in multiple roles within R&D in Semiconductor frontend design and system architecture, and within product management, with a consistent focus on image processing solutions.
Rajesh Mandamparambil, Senior Technical Leader in Advanced Semiconductor Packaging and Heterogeneous Integration, NXP Semiconductors
Abstract
Heterogeneous integration has emerged as a critical enabler for continued system-level scaling, performance differentiation, and supply chain resilience in the global semiconductor industry. As geopolitical dynamics increasingly shape technology access, industrial policy, and investment decisions, Europe faces both challenges and opportunities in strengthening its position across advanced packaging, chiplets, and system integration.
This presentation provides an industry perspective on how heterogeneous integration, spanning advanced substrates, assembly technologies, and system integration, can act as a strategic lever for Europe’s semiconductor ecosystem. It benchmarks Europe’s current capabilities against global leaders, highlights structural gaps across manufacturing, design enablement, and ecosystem coordination, and discusses where targeted investments and collaboration are most impactful.
Drawing examples from automotive high-reliability applications, the talk outlines how advanced packaging is evolving from a back-end activity into a system-level differentiator. The presentation concludes with key actions needed across industry, policy, and research to strengthen Europe’s long-term technological resilience and support sustainable semiconductor sovereignty.
Biography
Rajesh Mandamparambil is a senior technical leader in advanced semiconductor packaging and heterogeneous integration at NXP Semiconductors. He works on next-generation packaging platforms for automotive radar, high power, and high frequency applications, with a focus on system-level integration, chiplet-based architectures, and advanced assembly technologies. Rajesh plays an active role in ecosystem development, collaborating closely with suppliers, research institutes, and European R&D consortia to advance packaging innovation and technology readiness. He regularly contributes to industry forums, standardization discussions, and EU-funded programs, and is a frequent speaker on the strategic role of advanced packaging in enabling resilient and competitive semiconductor systems.
Alessandro Mapelli, Microsystems Engineer, Confovis
Abstract
As integration schemes move towards scalable manufacturing, process control must increasingly combine defect inspection with dimensional control without adding tool count, workflow complexity, and cost. Conventional approaches often separate inspection and metrology across different systems, complicating correlation and slowing yield learning.
We present a precision optical platform where image-based defect inspection and metrology share a single beam path, generating inherently co-registered datasets. The platform sets new standards by combining AOI with high-resolution 3D surface and sub-surface measurements based on our patented Structured Illumination Microscopy (SIM).
By extending SIM into the infrared, we introduce a complementary capability that leverages silicon transparency in the IR together with optical sectioning for non-destructive inspection and 3D metrology of wafer-to-wafer and die-to-wafer bond interfaces.
Biography
Alessandro Mapelli is a Microsystems Engineer at Confovis, where he focuses on adapting optical metrology and inspection solutions to the needs of the semiconductor industry. He holds a Master’s degree in Microengineering (2005) and a PhD in Microsystems and Microelectronics (2011) from the École Polytechnique Fédérale de Lausanne (EPFL). Before joining Confovis in 2022, he spent more than 15 years at CERN, where he led the development of advanced microfluidic cooling systems for pixel detectors and co-invented several patents in scintillation particle detection.
At Confovis, he is involved in defining performance validation protocols, developing technical content, and adapting Confovis’ technologies to advanced packaging, MEMS, and 3D integration applications.
Philippe Muller, Technology Scout, SUSS MicroTec
Abstract
Biography
Atsushi Nishikawa, Co‑Founder and CTO, ALLOS Semiconductors
Abstract
Growing gallium nitride (GaN) crystals on silicon facilitates a material that unlocks needed breakthroughs at the foundation of the AI megatrend. This becomes possible when strain-engineering the GaN crystals in such a way that the resulting 200 and 300 mm epiwafers can be processed with advanced semiconductor processes.
The use of GaN-based microLEDs as a light source for optical interconnects (OI) in AI datacenters allows, for example, replacing copper connections between xPU and high bandwidth memory (HBM), which today are limiting further computing power and energy-efficiency breakthroughs at the AI infrastructure level.
Next-generation displays, in particular AR/VR microdisplays, form the graphical interface with AI, which humans miss today. The required super high density of pixels per inch (PPI), high brightness, and energy efficiency are also achieved with GaN-based microLEDs.
To realize the enormous market potential of microLEDs, cost-effective integration of the microLED and “backplane” wafers with very high yield is essential. These “backplane” wafers contain the driver chips for the microLEDs and are manufactured in standard 200 mm and mostly in 300 mm CMOS fabs. In contrast, most microLED projects are realized in upgraded conventional LED factories on 150 mm sapphire substrates. Besides other issues, alone this wafer size mismatch would require solutions like die-to-die, die-to-wafer, or wafer reconstitution – each of which adds complexity, cost, and diminishes yield, while throughput might be very limited.
In this talk, we discuss the underlying technologies of ALLOS Semiconductors’ 200 and 300 mm epiwafer products and how these high-tech materials facilitate the cost-efficient integration of microLEDs with backplane wafers in CMOS fabs by supporting high-precision, high-yield processing and wafer-to-wafer bonding.
Biography
Dr. Atsushi Nishikawa is co‑founder and CTO of ALLOS Semiconductors, a deep tech company supplying gallium nitride (GaN) crystals grown on silicon for microLEDs. He brings over 25 years of experience in the growth of this crucial high-tech material, which is enabling breakthroughs for AI age displays and AI datacenter infrastructure. Before co-founding ALLOS, Dr. Nishikawa served as a Head of Epitaxy at AZZURRO Semiconductors, a pioneering supplier of GaN-on-Si epiwafers, and previously conducted advanced GaN research at NTT Basic Research Laboratories and worked on red GaN LEDs at Osaka University.
Dirk Panter, State Minister for Economic Affairs, Labour, Energy and Climate Action
Abstract
Biography
Born on February 7, 1974, in Achern, Germany, he studied Administrative Sciences at Leipzig University and gained international experience in Paris, Trawas (Indonesia), and Utrecht before working as an analyst and associate at J.P. Morgan in London, New York, and Frankfurt from 2000 to 2006. As a member of the SPD since 1997, he served in various leadership roles, including Executive Director and Secretary General of SPD Saxony, and has been a member of the Saxon Parliament since 2009, where he chaired the SPD parliamentary group from 2014 to 2024. In 2024, he assumed his current position as State Minister in the Saxon Ministry for Economic Affairs, Labor, Energy, and Climate Action. Beyond his political responsibilities, he has long served on the MDR Broadcasting Council, chairing its Budget Committee since 2015, and holds supervisory positions in cultural and sports organizations such as Leipziger Dok-Filmwochen and SC DHfK Handball.
Abdul Rahim, Ecosystem Manager, PhotonDelta
Abstract
This talk discusses how co-packaged optics (CPO) and next-generation pluggable modules are transforming optical connectivity for AI infrastructure. It will highlight the key underpinning technologies, including advances in photonic integration, high-speed modulators and light sources, and their heterogeneous integration within advanced photonic chip technology stacks. Together, these developments enable high-bandwidth, energy-efficient data movement across scale-up and scale-out systems.
Biography
Dr. Abdul Rahim is an expert in integrated photonics, managing an ecosystem of over 70 organisations at PhotonDelta since 2024. He holds a PhD in silicon photonics from TU Berlin and a degree in innovation management from HEC Paris. His career spans research roles at various renowned organisations. In his last assignment, he transformed the world’s first MPW broker of silicon photonics - ePIXfab - into a silicon photonics alliance. Since 2020, he has co-led the silicon photonics chapter of the Integrated Photonics Systems Roadmap – International. Recognised as a Photonics100 honouree in 2024, he is passionately shaping the future of photonics.
Gamal Refai-Ahmed, Senior Fellow and Chief Thermo-Mechanical Architect, AMD
Abstract
Biography
Dr. Refai is currently an AMD Sr Fellow, Distinguished Alumni of the University of Waterloo, Executive Technologist, and Visiting Faculty Professor, SUNY of Binghamton. Gamal's research and engineering practice areas are the thermal management of electronic and optical packaging, where he developed innovative electronic/optical packaging products at Xilinx, GE Research, AMD, Nortel, Astec-Emerson, Cisco, Ceyba, and ATI Technologies. he was the author of 120+technical papers and 130+ International Patents/ pending patents.
In 2010, Gamal was awarded the Calvin Lecture Award, and in conjunction with this latest recognition, his ASME Fellow grad was elevated to the ASME Life Fellow. In 2014, he was awarded the R.H. Tanner Industry Leadership Award by IEEE Canada for his industrial leadership of electronics packaging in Canada.
He was elected as a Fellow in the Canadian Academy of Engineering, in recognition of his leadership in promoting best electronics packaging and thermal management engineering practice in Canada. Also, He was elevated to Fellow in IEEE and was elected Fellow in EIC. He is the recipient of the Binghamton SUNY Presidential Medal. He is a recipient of the University of Waterloo Professional Medal.
Gamal was an adjunct professor at the University of Toronto and distinguished fellow at Ryerson University, and Visiting Faculty SUNY Binghamton.
Vishal Saroha, Technology & Market Analyst, Semiconductor Equipment, Yole Group
Abstract
Biography
Vishal Saroha is a Technology & Market analyst at Yole Group, where he focuses on market intelligence and consulting activities on semiconductor equipment, manufacturing, and the global supply chain. Prior to Yole, he worked at GlobalFoundries in Dresden as a Senior Integration Engineer, driving device and SRAM optimization for their 22FDX technology platform. Prior to that, he also has experience at IMEC in Belgium, where he worked on 3DIC integration and device reliability. Vishal holds a master’s degree in Nanotechnology from KU Leuven and a bachelor’s degree in Physics from the University of Delhi.
Alireza Shamsafar, Senior Principal Scientist, Smart Photonics
Abstract
Paths from discrete to monolithic integration have already happened for a lot of applications in the RF domain due to cost and performance optimisation, especially at lower frequencies, and some market segments realised mainly with RF CMOS process in larger wafer scales. However, for some applications and higher frequencies or electro-optical interfaces, chaplet or heterogeneous integration would be unavoidable due to the cost and performance advantage of each technology platform. For example, looking at EO modulator integration, which requires optical and RF driver chiplets or heterogeneous integration is needed at a lower frequency. This typically happens by using bond wire and flip chips at higher frequencies, but moving to frequencies above 130 GHz, 3RLD or other types of integration. Looking specifically at the technology side, RF InP so far is the fastest technology which also same time lase the light at wavelengths.
Biography
Alireza Shamsafar received the PhD degree in microwave engineering from Università Della Calabria, Rende, Italy, in 2013. From 2013 to 2014, he was a Researcher with the Micro Lab, University of Calabria. He was with the Huawei Technologies Microwave Competence Centre, Milan, Italy, from 2014 to 2016, and then he joined Ampleon Netherlands, Nijmegen, focusing on the design of millimetre- and submillimeter-wave integrated circuits and systems in SiGe, GaAs and GaN technologies, as well as nonlinear device characterisation and modelling for high-frequencies application till 2021. From 2020 to 2022, he was with Infineon Germany Munich as a PA technical lead, working on technology development and multi-chip module design mainly for 5G applications. From 2022 to 2023, he was with Ericsson Germany working as a technology expert regarding PA module development for 6G applications. He is currently with Smart Photonics, Eindhoven, as Senior Principal Scientist, working on electro-optical integrated circuits. His main research interest is above 100GHz optical components design and high-frequency interconnection between the RF driver or TIA and the optical modulator/receiver. He has several Journals and conference papers, and in 2013, he was a recipient of the 2013 GaAs Association Fellowship Award for his paper on integrated miniaturized power combiner.
Nava Shpaisman, Strategic Collaboration Manager, KLA
Abstract
As Advanced Packaging has evolved from providing simple protection and connection to the outside world to being an integral part of semiconductor system performance, process control requirements have been rapidly evolving as well in order to enable new process technologies. One particularly important emerging packaging technology is the use of W2W and D2W hybrid bonding for die stacking rather than making interconnections with conventional solder-containing microbumps. This new method is driving the adoption of process control methodologies and tools that are more similar to front-end semiconductor manufacturing than packaging assembly. In addition, entirely new inspection and metrology techniques may be required. In this presentation, the speaker will cover both the known technologies and challenges of hybrid bonding as well as process control methods and requirements that are being developed to assure high-yielding and reliable performance of the hybrid bonded die.
Biography
Nava Shpaisman is the strategic collaboration manager for panel-related products at KLA, overseeing global customer partnerships and advancing KLA solutions for next-generation FOPLP, ICS, and PCB technologies. Prior to joining KLA, she was Director of Chemistry at JetCu, a printed electronics startup, overseeing R&D and customer relations. Earlier, Nava worked as a senior researcher in tissue engineering at the New Jersey Biomaterial Center at Rutgers University. She holds a Ph.D. in materials science and an MBA in marketing from Bar-Ilan University, Israel.
Joerg Siegert, Director for Wafer Level Integration, amsOSRAM AG
Abstract
The scaling of bandwidth and energy efficiency is a key challenge for modern datacenters. Optical datacom systems offer significant advantages over conventional electrical interconnects and increasingly rely on heterogeneous integration of photonic emitters and detectors with high-speed electrical interconnects. High-density silicon interposers with through-silicon vias (TSVs) provide a critical enabling platform by combining dense routing, controlled electrical behavior, and compatibility with advanced integration schemes.
This presentation describes the development of a TSV silicon interposer platform for optical datacom transmitter applications. System requirements, interposer architecture, and materials stack are discussed with emphasis on electrical performance and manufacturability. Interposer performance is evaluated using integrated electrical test structures, enabling systematic characterization of DC resistance, parasitic effects, and high-frequency signal integrity. Measurement results are presented to highlight design tradeoffs and optimization paths. Concepts for stacking microLED emitters onto the interposer are presented, demonstrating the extensibility of the platform and its suitability for future heterogeneous integration.
Biography
Joerg Siegert is Director for Wafer Level Integration at amsOSRAM AG, where he leads the Wafer Level Integration team within Technology Development. He has been working on 3D and heterogeneous integration technologies since 2008, with a focus on TSV-based integration and advanced wafer-level process platforms.
He studied physics at Graz University of Technology, Austria, and KTH Royal Institute of Technology, Stockholm, Sweden, where he earned his PhD.
Jessica Stubbe, Global Application Manager, MKS Atotech
Abstract
Biography
Dr. Jessica Stubbe is Global Application Manager in Semiconductor at MKS’ Atotech in Berlin, where she leads the application team for electrochemical deposition in advanced packaging. She holds a PhD in coordination chemistry with a focus on electrochemistry and has developed a strong expertise in linking fundamental material behavior with process performance. Over the past years, she has focused on the development and optimization of plating processes for semiconductor applications, supporting global customer projects and bridging R&D with high-volume manufacturing. Her role combines technical expertise, customer collaboration, and strategic project leadership.
Dominik Suwito, Director for Process Engineering, Adeia
Abstract
Hybrid bonding is emerging as a key enabler for the next generation in advanced packaging technology, which is at the heart of the AI hardware revolution. The semiconductor supply chain is increasingly using hybrid bonding in high-volume manufacturing. The pursuit of yield improvement continues in this nascent technology to aid in the proliferation of this technology for high-value 2.5D and 3D packages. Such packages include high-performance compute (HPC) modules with chiplet architecture and high bandwidth memory (HBM) with 12 to 16 die stacks. When hybrid bonding was introduced many years ago, one criticism that still remains today was the difficulty of reworking parts in a hybrid bonding assembly flow.
In this presentation, we report our recent breakthroughs at Adeia in reworkable hybrid bonding. We will discuss the key factors necessary for high-yield rework processes and compare two debonding methods with respect to performance and suitable applications. Both debonding techniques preserve the surface topography, including surface smoothness and copper recess, so that the re-worked bond site can be repopulated with our standard assembly procedures. To assess bonding defects, we used confocal scanning acoustic microscopy (CSAM), and electrical probing of test vehicles with >30k interconnects within one die. We compare the yield between the first bond and the re-bond sites. Electrical pass yields of 98-100% were achieved on re-bond sites, demonstrating the promise of this technique. Finally, we share the potential process flow to implement a rework process within a hybrid bonding assembly process.
Biography
Dominik Suwito is Director for Process Engineering at Adeia, a technology company with a long history in Advanced Packaging and a pioneer in Hybrid Bonding. Dominik joined Adeia in 2019 and has since been overseeing process development and tech-transfers to licensees for Adeia’s wafer-to-wafer and die-to-wafer hybrid bonding technology. He develops technology in nano-scale surface engineering, hybrid bond interconnect integration, die stacking and thermal budget constraints.
Dominik studied physics at Ludwig Maximilian University in Munich and at Albert Ludwig University in Freiburg, and he wrote his PhD thesis at Fraunhofer ISE in Freiburg with a focus on silicon carbide for the surface passivation of silicon solar cells. Prior to Adeia, Dominik worked at First Solar, developing and transferring innovative solar cell manufacturing processes from the lab to HVM. At Tesla, he worked on overcoming manufacturing challenges for Tesla’s Solar Powered Roof Tile program. Dominik holds over 10 granted and pending patents.
Nicole Tien, Senior Technical Program Manager, ASE Europe
Abstract
As AI workloads continue to scale at an unprecedented pace, the demands placed on semiconductor packaging have reached a critical inflection point. This presentation examines how advanced packaging technologies are being reimagined to meet the exponentially growing requirements for compute power, memory bandwidth, and energy efficiency that modern AI infrastructure demands.
At the center of this evolution is Co-Packaged Optics (CPO), an approach that integrates optical and electrical components within a single package to overcome the bandwidth and power limitations of conventional electrical interconnects. During her presentation, Nicole Tien will explore how CPO enables bandwidth scaling from 1.6Tbps to beyond 32Tbps while delivering dramatic reductions in energy consumption, making it an essential enabler for the next generation of AI hardware.
Nicole will then guide the audience through the key engineering challenges at the frontier of CPO development, including 3D integration, fiber connectivity, precision optical alignment, and multi-stage testing methodologies. She will introduce breakthrough solutions and highlight ASE’s innovations driving end-to-end CPO assembly and the company's Known Good Optical Engine (KGOE) validated solutions, a framework purpose-built to deliver reliability and yield at scale for AI-era deployments.
Biography
Nicole Tien is a Senior Technical Program Manager at ASE Europe, where she drives advanced packaging technology development and innovation to support customer growth and ecosystem collaboration. She focuses on high-performance heterogeneous integration, including multi-die and 3D packaging solutions, enabling improved system-level performance, bandwidth, and energy efficiency. Nicole works closely with customers and industry partners to translate emerging requirements into scalable packaging solutions, supporting applications across AI, automotive, and high-performance computing. She is actively involved in advancing packaging strategies that push the limits of thermal, electrical, and mechanical performance, helping to enable next-generation semiconductor systems
Thomas Uhrmann, Vice President of Sales, EV Group
Biography
Dr. Thomas Uhrmann is Vice President of Sales at EV Group (EVG), a position he assumed in 2025. In this role, he is responsible for leading EVG’s global sales organization and driving growth across key markets worldwide.
Prior to his appointment as Vice President of Sales, Dr. Uhrmann served as Director of Business Development at EV Group, where he oversaw all aspects of the company’s worldwide business development activities. His focus included 3D integration, Advanced Packaging, and a number of emerging markets.
He holds an engineering degree in mechatronics from the University of Applied Sciences in Regensburg and earned a PhD in semiconductor physics from the Vienna University of Technology.
E. Jan Vardaman, President and Founder, TechSearch International, Inc.
Abstract
Biography
E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She was the editor of Recent Developments in Tape Automated Bonding, published by IEEE Press. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow. She is a member of MEPTEC, SMTA, and SEMI.
She serves on the JEDEC Task Force JESD-94 Working Group Application Specific Qualification Using Knowledge-Based Test Methodology. She has served on the IEEE CPMT Board of Governors for two terms. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium. She received her M.A. from the University of Texas, in 1981.
Nicolai Walter, Co-Founder and CEO, Pixel Photonics
Abstract
Co-packaged optics (CPO) is a key enabler for scaling bandwidth and energy efficiency in next-generation systems. This is especially true for quantum applications, where loss budgets are tight and every photon counts. In this context, scalable, high-efficiency photonic detection remains a critical bottleneck.
We present ARCTIC, a scalable platform for integrating superconducting nanowire single-photon detectors (SNSPDs) into photonic systems. By combining near-unity detection efficiency and ultra-low noise with wafer-scale, foundry-compatible fabrication, ARCTIC brings single-photon detection into high-volume manufacturing.
We further explore how co-packaging principles extend into the cryogenic domain through integration with cryo-electronics, enabling new system architectures.
ARCTIC paves the way for scalable quantum photonics, optical interconnects, and energy-efficient data processing.
Biography
Nicolai Walter is Co-Founder and CEO of Pixel Photonics, a company developing scalable single-photon detectors for next-generation photonic systems. He studied physics at the Karlsruhe Institute of Technology (KIT) and conducted his doctoral research at the University of Münster under Prof. Wolfram Pernice, where he helped pioneer waveguide-integrated superconducting nanowire detectors for quantum applications.
Recognizing the lack of scalable, highly efficient light detection solutions for industrial use, he co-founded Pixel Photonics in 2020 to translate this technology from research into manufacturable products. Today, he focuses on enabling wafer-scale, foundry-compatible photonic detection solutions, supporting applications in quantum technologies, optical communications, and advanced system integration.
Jean-Marc Yannou, Strategy & Innovation, Murata
Abstract
Silicon capacitors have emerged as widely acclaimed building blocks in advanced electronic systems, combining exceptional miniaturization with significant performance enhancements. These enhancements manifest differently across applications—ranging from improved electrical and RF behavior to superior thermal management, integration density, and long‑term reliability. In this presentation, we will outline why silicon capacitors have become indispensable in several critical functions within data-centre infrastructures, including optical transceivers, voltage‑regulator modules, and the power‑delivery networks embedded within the 3D packages of AI‑core processors. Particular emphasis will be placed on their insertion in 3D‑integrated systems, examining both current architectures and anticipated future evolutions. Finally, we will discuss the competitive landscape surrounding the development and supply of silicon‑capacitor technologies, highlighting how Europe thrives in this ecosystem and shapes it.
Biography
Jean-Marc Yannou is VP Strategy & Innovation at Murata for integrated passive solutions, based in France. Jean-Marc has a 30-year experience in the semiconductor industry, serving varied functions ranging from test engineering to design to innovation management, marketing and sales. He especially developed an expertise in semiconductor packaging via various positions at TI, NXP, Yole Development and ASE. Jean-Marc has been an active member of IMAPS for 20 years. He was elected President of the IMAPS France chapter from 2010 to 2014. Finally, he chaired EMPC (the European Microelectronics & Packaging Conference) in Grenoble, France, in September 2025 on behalf of IMAPS Europe.