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Session 12Advanced Metal Structures

Chairs: Marc Bergendahl, IBM Research; Goswami, Shubhodeep, GE Global Research; Rob Pearson, Rochester Institute of Technology

This session begins with a discussion of improved reliability of sub-micron through silicon vias and continues with contrasting polysilicon fuse voiding mechanisms. The session continues with an additional metal line stress voiding paper and concludes with a discussion of multi-level bond pad structural and electrical design trade-offs.


12.1   Nano Ni/Cu-TSVs with an Improved Reliability for 3D-IC Integration Application

M. Murugesan, K. Mori, H. Hashimoto, J.C. Bea, T. Kojima, T. Fukushima, and M. Koyanagi Global INTegration Initiative (GINTI), NICHe, Tohoku University


12.2 Polysilicon Fuse Electrical Voiding Mechanism

Gang Liu, Rommel Relos, Bohumil Janik, Robert Davis, Tracy Myers, Derryl Allman, Jeff Hall, Steven Vandeweghe, Santosh Menon, Ed Flanigan, ON Semiconductor


12.3 Aluminum Voiding and Delamination Induced by High Intrinsic Stress

Cindy Daigle, Michelle Beauchemin, Thomas Moutinho, Christopher Qualey, Texas Instruments


12.4  Bondpad Design Structural vs. Electrical Tradeoffs

Brett Williams, Robert Davis, Justin Yerger, Derryl Allman, Bruce Greenwood, Troy Ruud, ON Semiconductor


Networking Break

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