Wafer Geometry Control for Advanced Semiconductor Manufacturing
By James Amano, SEMI
The SEMI Standards Silicon Wafer Committee has been the foundation of the SEMI Standards Program for over 40 years, developing critical standards for wafer specifications, metrology, and material characteristics. While recent focus has been on development of 450mm related standards, critical work still remains to be done that is not specific to wafer diameter. While industry collaboration on measurement methods for wafer geometry, bulk metals, stress, surface particles, and crystal characterization has enabled silicon wafer development and high volume manufacturing wafer quality control to keep pace with Moore’s Law, the relentless reduction in feature sizes in semiconductor manufacturing increasingly makes it difficult to perfect processes with high yield and high uniformity. These process challenges require that variation of the geometry of the wafer be controlled and monitored throughout the process flow. While wafer geometry standards have typically focused on the quality of the starting bare wafer, it is equally important today to monitor and control process-induced wafer geometry changes.
To introduce the challenges that lay ahead, SEMI is pleased to host the upcoming Wafer Geometry Control for Advanced Semiconductor Manufacturing seminar, to be held in conjunction with SEMICON West 2014, on July 9, in the San Francisco Marriott Marquis Hotel. Authoritative customers, including IBM, Intel, and Micron, will present recent developments and future needs for advanced semiconductor manufacturing.
Topics to be presented include:
Wafer Edge Roll-Off (ERO) Characterization: Wafer ERO is a critical wafer geometry characteristic. Primary ERO metrics, ERO impact on device processes, and the importance of ERO characterization to wafer flatness improvement in recent years will be introduced, along with key challenges in the future wafer flatness development are also shared.
Figure 1: Components of ERO and global bending (SEMI M77)
Role of Process-Induced Wafer Geometry in Advanced Semiconductor Manufacturing: Process-induced wafer geometry (PIWG) can result from processes such as deposition, etching, annealing, and planarization, and can negatively affect overlay and focus in lithography, uniformity in chemical-mechanical polishing, and yield and alignment in wafer bonding processes for 3D integration. Multiple scales of PIWG and how uniform and non-uniform stress changes can affect the geometry of the wafer will be presented. The effect of PIWG on lithography, CMP, and wafer bonding processes will be examined through a combination of mechanics models that demonstrate the underlying physics of PIWG effects in processes as well as experimental data that illustrates the impact on real wafers.
Technologists scheduled to speak include:
- Dr. Joann Qiu, Senior Technologist, Intel
- Dr. Oleg Gluschenkov, IBM
- Dr. Kevin Turner, Director, Wolf Nanofabrication Facility, University of Pennsylvania
- Micron (speaker TBD)
- Dr. Jaydeep Sinha, Wafer Inspection Group, KLA-Tencor
Proposals discussed during this workshop will be considered for standardization by the SEMI Standards Advanced Wafer Geometry Task Force under the Silicon Wafer Committee. To register for the Standards workshop at SEMICON West, please visit: http://www.semiconwest.org/node/12066
Meeting schedules for the Silicon Wafer and its task forces are online at: http://www.semi.org/en/node/39061
SEMI, Standards Watch - June 2014