SMC 2013 Abstract - Chris Bishop, Micron Technology
Characterization and Metrology Challenges for Emerging Memory Technology Landscape
Naga Chandrasekaran, Steve Hues, Shifeng Lu, Du Li, and Chris Bishop
Traditional Memory devices (DRAM, NAND, NOR) continue to broaden their application space enabled by a combination of density increase through technology shrink and performance improvements through materials innovation. At the same time, cadence of continued scaling for traditional memory devices is slowing down as they face critical limitations1. One of the primary limitations is due to the fact that these devices rely on charge (electron) trapping to hold memory information. In the case of NAND FLASH device, as the technology node shrinks from 4X nm to 1X nm [Figure 1], the numbers of electrons that may be stored in the floating gate diminish to the point where device reliability is degraded and continued scaling becomes difficult. In the case of DRAM, refresh performance requirements continues to challenge capacitor aspect ratio and material choices for the structure. Other factors limiting scaling include state of equipment technology to pattern smaller features and ability to achieve a competitive cost structure.
Such critical limitations of traditional memories are being overcome by three parallel approaches: (1) Traditional 2-D memory technologies are starting to transition to 3-D structures (2) emergence of novel emerging memory technologies (PCM, STTRAM, Resistive RAM, to name a few) and (3) integration of multiple memory and CMOS technologies on board to facilitate multiple functions through innovative system architecture introductions. These innovative approaches are driving new and unique technology challenges in memory development space. One such area, which is exponentially challenged by such advances, is materials and structural characterization.
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