SEMI 3DS-IC Committee Approves New Standards on Thin Wafer Handling and Inspection & Metrology
By Paul Trio, SEMI Standards
At the North America (NA) Standards Spring 2013 meetings, the NA 3DS-IC Committee approved two new guides on inspection & metrology and another on thin wafer handling:
- SEMI Draft Document 5175, New Standard: Guide for Multi-Wafer Transport and Storage Containers for 300 mm, Thin Silicon Wafers on Tape Frames
- SEMI Draft Document 5409, New Standard: Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks
- SEMI Draft Document 5410, New Standard: Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures
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SEMI Draft Document 5175
For the last few decades, the semiconductor industry has been following Moore’s Law effectively which has resulted in significant miniaturization of transistors and on chip logic circuitry. Below the 28 nm node, as design complexity of the IC (Integrated Circuits) increases, cost and risk associated with these designs could become prohibitive for many companies. Three dimensions (3D) die stacking methodology offers unique advantages of low power and high bandwidth per watt without increasing the cost significantly. The majority of the semiconductor industry has been evaluating various approaches to integrate different ICs on active or passive interposers. Some of these solutions are already being used in product, albeit at relatively low volumes compared to standard assembly techniques such as wire bond and flip chip assembly.
However, as the market need for 3D IC grows, the complexity of the supply chain will increase and thin silicon wafers (50 µm to 200 µm), active or passive, will have to be moved from one location to the other for assembly. Currently there is limited data available from initial products that have been launched in the last few years and there is a need to establish minimum guidelines to ship such delicate wafers without creating any defects during shipment.
Document 5175 was developed by the Thin Wafer Handling Task Force to provide the 3DS-IC community with the tools needed to ship thin wafers for use with 3D stacking applications.
This Guide is intended to address the needs for choosing a method for shipping thin wafers on tape frames in such a way that they arrive undamaged at their final destination. It describes various methods of shipping thin wafers on tape frames.
Shipping thin wafers without damage requires the use of appropriate transport and storage containers because of several interacting factors, the most important of which are listed in this Guide.
Figure 1: Examples of Methods for Shipping Thin Wafers on Dicing Frames
SEMI Draft Document 5409
Control of parameters, such as bonded wafer stack (BWS) thickness, total thickness variation (TTV), bow, warp/sori, and flatness metrology, is essential to successful implementation of a wafer bonding process. These parameters provide meaningful information about the quality of the wafer thinning process (if used), the uniformity of the bonding process, and the amount of deformation induced to the wafer stack by the bonding process. Total thickness variation is also critical in certain bonded wafer manufacturing process steps, since non-planarity can lead to problems in subsequent processing steps, including lithographic overlay and intermittent electrical contact between metal layers in the bonded wafers. Developed by the Inspection & Metrology Task Force, this Guide provides a description of tools that can be used to determine these key parameters before, during, and after the process steps involved in wafer bonding.
Figure 2: Bonded Wafer Pair Following TSV Formation and Wafer Bonding Operation
Figure 3: Temporarily Bonded Wafer Pair--Device Wafer is Edge-Trimmed and Thinned
SEMI Draft Document 5410
Developed by the Inspection & Metrology Task Force, this Guide aims to assist in the selection and use of tools for performing measurements of geometrical parameters of an individual TSV (through-silicon via), or of an array of TSVs. TSVs are expected to be a critical element in future three-dimensional stacked integrated circuit (3DS-IC) packaging. Advanced TSV designs with higher aspect ratios and smaller diameters may challenge TSV metrology techniques. This Guide also addresses the various metrology techniques that are currently available that enable TSV (through-silicon via) dimensional measurements. This Guide can also assist producers and users of TSV metrology to develop products and conduct meaningful evaluations.
Figure 4: Sketch of a TSV Showing Some Geometrical Properties of Interest for TSV Metrology
Pending successful procedural review, Documents 5175, 5409, and 5410 will be the third, fourth, and fifth 3DS-IC Standards published by SEMI.
SEMI published its first 3DS-IC Standard in September 2012. SEMI 3D1, Terminology for Through Silicon via Geometrical Metrology, was developed to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV). In early 2013, SEMI published its second 3DS-IC Standard as SEMI 3D2, Specification for Glass Carrier Wafers for 3DS-IC Applications. This specification is intended to address the needs of the 3D Stacked IC (3DS-IC) industry by providing the tools needed to procure pristine glass carrier wafers to be used in a 3DS-IC process.
SEMI 3DS-IC Standardization Activities Continue
Bonded Wafer Stacks Task Force
The Bonded Wafer Stacks Task Force will continue development of SEMI Draft Document 5173C, New Standard: Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack which failed technical committee review based on inputs received from the Cycle 1 voting period. The task force plans to reballot this document as 5173D for the Cycle 3 or Cycle 4, 2013 voting period.
The task force is also continuing its work on SNARF # 5174, New Standard: Specification for Identification and Marking for Bonded Wafer Stacks.
Finally, at the NA Standards Spring 2013 meetings, the task force received committee approval to develop a proposal to revise SEMI 3D2 as SNARF #5588. Ballot 5588 is scheduled to be submitted for the Cycle 3, 2013 voting period.
Inspection & Metrology Task Force
With Documents 5409 and 5410 passing technical committee review, the Inspection & Metrology TF will continue its work on the following standardization activities:
- New Standard: Guide for Measuring Voids in Bonded Wafer Stacks (SNARF # 5270)
- New Standard: Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures (SNARF # 5447)
- New Standard: Test Method for Measuring Warp, Bow and TTV on Silicon and Glass Wafers Mounted on Wire Grids by Automated Non-Contact Scanning using Laser Scanning Interferometry (SNARF #5506)
Taiwan 3DS-IC Activities
The Middle End Process TF formalized its standardization efforts in 2012 via SNARF # 5473 (New Standard: Guide for Alignment Mark for 3DS-IC Process) and SNARF # 5474 (New Standard: Guide for CMP and Micro-bump Processes for Frontside TSV Integration).
In early 2013, the task force completed its work on SEMI Draft Document 5474 and was submitted for the Cycle 2, 2013 voting period for Letter Ballot distribution.
In order to speed up volume production of 3DS-IC products, a generic middle-end process flow is needed to communicate the frontend and backend processes. The quality criteria and metrology methodology of the key modules such as TSV, chemical mechanical planarization (CMP), and micro-bump are developed to ensure high-yield of the middle-end process. Document 5474 was developed to provide a generic middle-end process flow to define acceptable TSV and CMP quality criteria as well as to develop methodology and measuring procedures for micro-bump. The Guide provides criteria and common baselines of the middle-end process for related upstream and downstream manufacturers in fabricating 3DS-IC products.
The North America 3DS-IC committee and its task forces will meet face-to-face in conjunction with the NA Standards meetings at SEMICON West 2013 in San Francisco, California. For more information and to register for these meetings, please visit the SEMI Standards website. For more information about SEMICON West 2013, visit www.semiconwest.org.
SEMI, Standards Watch - May 2013