SEMI 3DS-IC Committee Approves New Specification for Glass Carrier Wafers
By Paul Trio, SEMI
At the SEMI North America Standards Fall 2012 meetings, the NA 3DS-IC Committee approved SEMI Draft Document 5482, New Standard: Specification for Glass Carrier Wafers for 3DS-IC Applications.
Developed by the Bonded Wafer Stacks Task Force, this specification is intended to address the needs of the 3D Stacked IC (3DS-IC) industry by providing the tools needed to procure pristine glass carrier wafers to be used in a 3DS-IC process.
SEMI Draft Document 5482 describes dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state. This specification also describes glass carrier wafers with nominal diameters of 200 and 300 mm, and a thickness of 700 nm, although the wafer diameter and thickness required may vary due to process and functional variation. Such variations shall be clarified in the purchasing order or in the contract. Methods of measurements suitable for determining the characteristics in the specifications are also indicated.
After being approved by the NA 3DS-IC Committee, ballot 5482 has since been submitted to the Audits & Reviews Subcommittee where it also passed procedural review. SEMI expects to publish Document 5482 as SEMI 3D2 in early 2013. 3D2 is the second 3DS-IC standard published by SEMI. SEMI 3D1, Terminology for Through Silicon via Geometrical Metrology, was published in September 2012 and was developed to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV).
SEMI 3DS-IC Standardization Activities Continue
The NA Three-dimensional Stacked Integrated Circuits (3DS-IC) Committee and its associated task forces (TFs) met on October 30 in conjunction with the NA Standards Fall 2012 meetings in San Jose, California.
Bonded Wafer Stacks Task Force
In addition to the development of SEMI Draft Document 5482, the Bonded Wafer Stacks Task Force will continue development of SEMI Draft Document 5173B, New Standard: Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack which failed technical committee review based on inputs received from the Cycle 6 voting period. The task force plans to reballot this document as 5173C for the Cycle 1, 2013 voting period. The task force will also continue it so work on SNARF # 5174, New Standard: Specification for Identification and Marking for Bonded Wafer Stacks.
Inspection & Metrology Task Force
The task force received committee approval to develop a new test method for measuring warp bow, and TTV on silicon and glass wafers as SNARF # 5506.
Current metrology strategies have evolved from methods used to characterize smaller, lower aspect ratio geometries. Conventionally, three point mounts have been used to measure flatness/warp of wafer along with the gravity compensation.
For instance 3DS-IC applications use larger and thinner wafers than conventional applications. Large, thin wafers have inherently low stiffness, leading to large deflections, which make compensation more challenging. Ball mounts cause large deflections, 4-point and ring supports have redundant support and are sensitive to how parts are placed on the mount.
The industry therefore would benefit from identifying an alternate test method that better reflects the application usage of these wafers. One such approach used in the industry is a similar set up to Sori with a wire mount and a noncontact scanning method that allows depicting a complete picture of the wafer’s shape and dimensional parameters.
SNARF # 5506 will lead to the development of a new test method that accurately and reliably depicts the dimensional shape of single silicon and glass wafers that are ≥ 300 mm in diameter and ≤ 775 µm in thickness and that uses a wire mount and Laser scanning interferometry. This method will recommend the wafer to be characterized in a position that allows for a free state profile measurement on a flat surface. The document will include applicable ranges for valid measurements where possible.
The Inspection & Metrology TF will also continue its work on the following standardization activities:
- New Standard: Guide for Measuring Voids in Bonded Wafer Stacks (SNARF # 5270)
- New Standard: Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures (SNARF # 5410)
- New Standard: Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures (SNARF # 5447
SEMI Draft Document 5410 is scheduled to be submitted for the Cycle 1, 2013 voting period.
Thin Wafer Handling Task Force
The Thin Wafer Handling TF is nearing completion in its development of SEMI Draft Document 5175, New Standard: Guide for Multi-Wafer Transport and Storage Containers for 300 mm, Thin Silicon Wafers on Tape Frames. Ballot 5175 is scheduled to be submitted for the Cycle 1, 2013 voting period.
Taiwan 3DS-IC Activities
The Middle End Process TF formalized its standardization efforts via SNARF # 5473 (New Standard: Guide for Alignment Mark for 3DS-IC Process) and SNARF # 5474 (New Standard: Guide for CMP and Micro-bump Processes for Frontside TSV Integration). The task force plans to submit SEMI Draft Document 5474 for balloting in early 2013. The Testing TF also received approval to begin work on a new guide for Incoming/Outgoing Quality Control and Testing Flow for 3DS-IC Products as SNARF # 5485. For more information about the Taiwan 3DS-IC activities, please contact Ms. Catherine Chang (email@example.com) at SEMI.
SEMI, Standards Watch, December 2012