3D IC Standardization Underway at SEMI
3D-IC Standardization Underway at SEMI
By James Amano, Director, International Standards, SEMI
Given their potential for increased performance, smaller footprints, and reduced cost and power consumption, 3D-IC technologies are now on the leading edge of innovation, with the industry poised to jump from concept to commercialization. However, multiple manufacturing challenges must first be solved, as 3D-ICs' increased design and mechanical complexity can lead to increased manufacturing defects, as well as thermal management issues and signal interference. While 3D integration using through-silicon vias (TSVs) promise a fundamental shift for current multi-chip integration and packaging approaches, cost-effective, high-volume manufacturing will be difficult to achieve without standardized equipment, materials, and processes.
The needs and opportunities for 3D-IC manufacturing standards were first explored at SEMICON West in 2010, and the first 3DS-IC SEMI Standards Committee was formed in North America late last year. After a kick-off meeting in January, the 3DS-IC committee met again during the recent NA Spring 2011 meetings and made further progress in targeting the Committee’s initial priorities. At the conclusion of the meetings, activities had been organized into three Task Forces (TFs): Thin Wafer Handling, Bonded Wafer Stacks, and Inspection and Metrology.
The Thin Wafer Handling TF aims to develop standards for reliable handling and shipping of thin wafers and dies (e.g., micro-pillar grid arrays, or MPGA) used in high-volume manufacturing. As part of this effort the TF will define thin wafer handling requirements including physical interfaces used in 3DS-IC manufacturing, as well as shipping requirements, including packaging, reliability, and other relevant criteria for both thin wafers and MPGAs.
The TF’s first effort is a guide for multi-wafer transport and storage containers for thin wafers. Current standards for shipping boxes, FOUPs, and FOSBs are not well-suited for the reliable storage and transportation of thin wafers and dice on tape frames used in 3DS-IC manufacturing. Wafer thicknesses of 30-200um will need significant changes to the current design criteria of current wafer transport and storage containers. This document will include specifications for tape frames, thin wafers on tape frames, container capacity requirements, and transportation/vibration and mechanical shock requirements.
Future topics for the Thin Wafer Handling TF could include shipping carriers for thin wafer (wafer cassette, box or frame), shipping carriers for dies (MPGA), and reliability test methods.
The Inspection and Metrology TF is working on standards to be used in measuring the properties of TSVs, bonded wafer stacks, and dies used in 3D IC manufacturing. Specific areas that have been identified to be in need of inspection and metrology standards include TSV physical properties (depth, top, bottom critical dimensions, side wall, etc.) and bonded wafer stack properties (overlay, bond inspection).
The Task Force’s will initially focus on the physical parameters of TSVs. Multiple different technologies exist for measuring various physical parameters of a single TSV or arrays of TSVs, such as pitch, top critical dimensions, top area, depth, and taper. However, currently it is difficult to compare measurements from the various technologies, as in some cases parameters are called by similar names but are different aspects of the same measurement. This standard will group the various technologies and allow for valid correlations and comparisons.
Additional candidates for standardization include whole wafer damage inspection (crack, break, etc.) at the macro level as well as inspection at the micro level (microbump, pad, etc.). The TF is working on a process flow map that identifies known, as well as potential, areas for metrology, and all members are encourage to identify areas where they can contribute.
The Bonded Wafer Stacks TF has two activities underway. The first is a specification for parameters, as existing wafer standards (such as SEMI M1: Specification for Polished Single Crystal Silicon Wafers) do not adequately address the needs of wafers used in bonded wafer stacks. Wafer thickness, edge bevel, notch, mass, bow, warp and diameters are changed when wafer stacks are bonded together, or when wafer stacks bonded and thinned. These deviations from wafer parameters specified in SEMI M1 have numerous impacts in other equipment and hardware standards that reference SEMI M1, and are the motivation for a new standard to reflect wafer parameters associated with bonded and bonded/thinned wafer stacks. This activity will include both silicon and glass carrier wafers.
Similarly, the wafer identification and marking needs of bonded wafer stacks are not covered by current standards. Locations currently used for ID marking (such as backside near notch in SEMI T7: Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol) will be removed during backside thinning operations or edge-trim operations, or buried under an opaque layer of silicon and rendered unreadable by optical readers when bonded. Multiple wafer stacks will combine wafers with multiple process history, including tracking of temporary carrier wafers, and a standard needs to be developed to combine and track bonded wafer stacks with multiple wafer histories.
Lastly, an additional new task force is being formed to work on standards for dimensions and sizes of carrier wafers as well as edge trimming of device wafers. The output of this task force will be used in the development of the bonded wafer stacks specification by the Bonded Wafer Stacks TF.
The above activities are just the beginning of what promises to be a global, industry-wide effort. Over 125 technologists from industry, research institutes, and academia around the world have already joined the SEMI 3DS-IC Standards Committee and are at work on these critical standards. The committee and task force will next be meeting at SEMICON West 2011 in July, and the Standards Program will also present a 3DS-IC Workshop to introduce the development and commercialization status of key aspects of TSV manufacturing and TSV integration. If you aren’t involved, now’s the perfect time - see you at SEMICON West!
About the SEMI Standards Program
Participation in the SEMI Standards Program is free, but requires registration. If you are not yet a member, please register at www.semi.org/standardsmembership
About 3D-IC Activities at SEMICON West
3D-IC technology is in the spotlight at SEMICON West 2011, with technical sessions, keynote presentations, and exhibitors all dedicated to products, technologies, and solutions for 3D-IC, including design, device fabrication, packaging, and test. For more information, please visit www.semiconwest.org/Segments/3DIC .
SEMI Standards Watch – April 2011
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