CAST Workshop Explores OEE and Key Contributors to Cost of Test

CAST Workshop Explores OEE and Key Contributors to Cost of Test

The Collaborative Alliance for Semiconductor Test held a workshop on March 8 at SEMI headquarters in Silicon Valley to explore critical issues in test and identify pre-competitive activities that can advance the industry.  The day was structured to provide CAST members from all sectors of the industry an opportunity to openly discuss cost-of-test issues in collaborative interactive format.

The day started with three presentations from industry leaders representing the IDM, Fabless and OSAT communities on the critical needs and opportunities for improvement in semiconductor test.  Dale Ohmart, Test Engineering manager at Texas Instruments, began the discussion by emphasizing that, despite the significant decrease in the costs of test as a percentage semiconductor revenues, test contribution’s to total semiconductor manufacturing costs continues to increase.  Ohmart showed industry statistics that while memory test costs declined by 50% in the last ten years, non-memory test costs have not shown such improvement.  Showing detailed data from TI operations, Ohmart demonstrated that memory has significantly benefitted from parallel test, while the high mix, lower volume and shorter test time operations outside of memory has not benefitted to the degree from advances in parallel test.  Multi-site testing has not been a “panacea” for operations like TI where product mix increases in diversity.
CAST was formed in 2008 by semiconductor device makers and test industry suppliers to engage in and resolve common industry issues related to higher test equipment utilization, lower costs, and greater standardization and return on test-related R&D. CAST members include a range of semiconductor industry leaders from automated test equipment (ATE) companies, integrated device manufacturers (IDMs) and outsourced semiconductor assembly and test (OSAT) companies. For more information on CAST, visit www.semi.org/CAST or email CAST@semi.org

In TI’s product mix, Overall Equipment Effectiveness (OEE) is the key metric in evaluating and managing the cost of test in their operations.  OEE is recognized as an industry standard used to represent equipment efficiency, but discussions revealed the metric is not consistently understood or applied to test.  Ohmart and TI see OEE as:

OEE = Total Time for Testing Good Units/Total Operating Time X 100

From a Pareto analysis of OEE factors, material flow issues comprise almost half of lost time causes (e.g. waiting for material to test).  Other limiting factors in OEE are product changeovers, set-up, handler jams, unscheduled downtime.  According to TI data, OEE is less impacted by the tester than by operational issues in scheduling and non-test dependencies.  Other key factors in the Cost of Test (CoT) are handlers and the loadboard/interface/socket specificities.

Seyed Paransun, director of Test, Amkor, reinforced the cost of test priorities for the outsourced test and packaging community.  Paransun sees IC volume growing at 10% annually for the next five years, both through “More of Moore” advances and “More than Moore” IC diversification.  These factors increase cost and productivity pressures on ATE and handlers, especially for OSATs like Amkor that have over 100 customers, manage 1,000+ testers and over 6,000 test programs. 

Amkor calculates that the tester itself represents 65% of the costs and thus great emphasis is placed on getting more out of tester investment, including greater parallelism and multisite test.  Automatic handling equipment costs and functionality has risen to become a major issue with Amkor.  Approximately 15% of Amkor’s capital spending in 2007 was devoted to handlers and in 2011 this percentage has grown to 34%.  More I/Os, finer pitches, multi-site, heat management, and other technical challenges have driven handling and interface costs beyond historical levels.

Paransun sees several opportunities for the industry to work together in addressing common problems.  Industry standards opportunities exist in software, especially data infrastructure, test cell management and yield diagnostics.  Standards may also be applicable in hardware, such as in contact methodology, and test processes in areas such as test methodology and test point insertion for 3D packaging.  Paransun sees that Standards can be good, but will probably only be implemented going forward on new products, not retroactively.

In addition, Paransun sees significant opportunity to increase the value of test by addressing emerging test challenges of 3D packaging.  Addressing the problem of limited access (similar to SIP or System In Package), such areas as improved data collection and standardized formats, support for IEEE 1149.7/1687, and addressing the testing of interconnects across stacked die will improve tangible value and relevancy to the industry.

Yield improvement is one of the biggest leverages on CoT.  “A one percent yield gain can result in up to a fifteen percent gain in CoT,” according to Paransun.

Scott Benner, director of Engineering at Qualcomm, also sees time-to-market and time–to-yield as critical performance factors for test operations.  According to Benner, Qualcomm uses a common motherboard & daughter card strategy where possible, especially on non-SoC products.  Test times are generally targeted at around 1 second and for multi-site, the optimal productivity is gained at around x8.           

Like the other speakers, Benner finds that handler efficiency is lagging the tester and impacting the test cell performance.  Custom solutions with dedicated layout requirements also increase costs and limit the ability to standardize.  Reinforcing earlier comments, Benner said Test Cell optimization is needed.

Other workshop discussions included a session on "Collaboration: What's Pre-competitive & What's Not" and "Design-to-Test."  Another significant part of the day was a review and interactive session on CAST Working Groups in the areas of STDF, Test Cell Communications and Adaptive Test.

As a working session of the CAST organization, a number of issue areas and action items were identified. The following list is a summary of important items:

  • Handler-Prober-Tester Interface: While CAST has a Working Group devoted to this area, renewed emphasis on this topic was identified for priority by session attendees
  • Quality Standards for interface performance: Every speaker identified this area as a source of common weakness in test operations and test methodology
  • Further define OEE elements for Test: A common measurement standard and greater understanding of the impact of test and non-test elements on OEE was agreed to be an opportunity for further examination.
  • Greater understanding of the value of Test: Despite Test’s contribution to yield improvements and yield ramp, as well as significant total cost reductions achieved over the past decade, the value of test is poorly articulated to the industry.  CAST agreed to examine publishing  a “Value of Test” White Paper and other actions that can improve the industry’s understanding of test’s contribution to financial performance

Overall, the Workshop delivered on its objective to provide a forum for interactive and productive discussions among test professionals to identify pre-competitive projects for consideration as CAST projects. It is anticipated that additional CAST Workshops will be scheduled on various topics.

For more information on CAST, visit www.semi.org/CAST or email CAST@semi.org

 

April 5, 2011