European 3D TSV Summit - Program
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| CONFERENCE AGENDA | ||||
| Tuesday 22 January | Platinium Sponsor:  Golden Sponsors:    Silver Sponsors:     Sponsors:       Logo Sponsors:         | |||
| 07:45 | Registration | |||
| 08:50 | Welcome SEMI | |||
| 09:00 |  | OPENING - Perspectives on 3D TSV Benefits in Microelectronics Applications Laurent Malier, CEO CEA-LETI | ||
| 09:25 |  | KEYNOTE - Advancing high performance heterogeneous integration through die stacking Suresh Ramalingam, Senior Director Packaging and Advanced Technology Development Xilinx | ||
| COST OF OWNERSHIP: Process, Equipment and Materials Innovations for Cost Effective Solutions Chairman: James Quinn, VP Marketing and Sales, Multitest | ||||
| 09:50 | 2.5 & 3D Enabling Technologies Selection Based on CoO & Technology Maturity Tradeoff Analysis Eric Beyne, Director of Advanced Packaging imec | |||
| 10:15 | Coffee Break - Exhibition venue | |||
| 11:00 | Production Solutions for Via Reveal Processes – Etch and CVD David Butler, VP Marketing SPTS | |||
| 11:25 | PVD Solutions for Under Bump and TSV Metallization with Higher Productivity for Future Device Generations Glyn Reynolds, Senior Scientist Oerlikon Systems | |||
| 11:50 | Innovation in Middle End Process Cu Via Reveal Laura Mauer, Director of Process Technology Solid State Equipment LLC | |||
| 12:15 | Lunch Break - Exhibition venue | |||
| 13:45 |  | KEYNOTE - The Future of Packaging: Advanced System Integration Ron Huemoeller, Senior VP Advanced Product Development AMKOR | ||
| TECHNOLOGIES: Critical Enabling Technology bricks Chairman: Albert Koller, VP and Head of Semiconductor, Oerlikon Systems | ||||
| 14:10 | 3D Integration Technologies – Enabling System in Package Solutions Jurgen Wolf, Department Head of HDI WLP/ASSID Fraunhofer- IZM / ASSID | |||
| 14:35 | Latest Insights in Material and Process Technologies for Interposer and 3D Stacking Rainer Knippelmeyer, CTO and VP of R&D, GM Product Line Bonder Suss Microtec | |||
| 15:00 | 3D IC – Recent Advances in Thin Wafer Processing and Chip Stacking Paul Lindner, Executive Technology Director EV Group | |||
| 15:25 | Advancements in Thin Wafer Handling Using the ZoneBOND® Process Tony Flaim, CTO Brewer Science | |||
| 15:50 | TSV Chip Stacking Meets Productivity Hannes Kostner, Director of R&D Datacon BESI | |||
| 16:15 | Coffee Break - Exhibition venue | |||
| MARKET BRIEFING - Powered by Yole Développement | ||||
| 17:15 | 2.5D interposer, 3DIC and TSV Interconnects Lionel Cadix, Market and Technology Analyst Advanced Packaging Yole Développement | |||
| 17:45 | Panel Discussion - 3DIC : Ready for high volume manufacturing? Moderators: Lionel Cadix, Yole Développement - Yann Guillou, SEMI Panelist: Ron Huemoeller, AMKOR Bradford Factor, ASE Jon Greenwood, GLOBALFOUNDRIES Heinz-Peter Wirtz, STATS ChipPAC | |||
| 18:30 | Networking Cocktail - Sponsored by Yole Developpement | |||
| 19:15 | Departure to Gala Dinner | |||
| 19:30 | Gala Dinner - Sponsored by AEPI and Rudolph Technologies | |||
| Wednesday 23 January | Platinium Sponsor: Golden Sponsors: Silver Sponsors: Sponsors: Logo Sponsors: | |||
| 08:00 | Registration | |||
| 08:30 | Welcome SEMI | |||
| 08:35 |  | KEYNOTE - 3D Integration for Mobile Applications Georg Kimmich, Head of Silicon Packaging R&D ST-Ericsson | ||
| DESIGN / TECHNOLOGY / APPLICATIONS CONSIDERATION Chairman: Thorsten Matthias, Director or Business Development, EV Group | ||||
| 09:00 | 3D-IC: Moore’s Law and Beyond – Design Infrastructure support to enable Moore’s Law and Beyond technology Brandon Wang, Director 3D IC and Advanced Technology Product Management Cadence Design System | |||
| 09:25 | 3D innovations: From design to reliable systems Uwe Knoechel, Group Manager Analog Design and System Integration Fraunhofer-IIS | |||
| 09:50 | From 3D Toolbox to 3D Integration: Examples of Successful 3D Applicative Demonstrators Nicolas Sillon, Head of 3D Integration CEA-LETI | |||
| 10:15 | Coffee Break - Exhibition Venue | |||
| PRODUCT MANUFACTURING Chairman: Martin Schrems, Director of R&D, ams AG | ||||
| 10:50 | 3D Silicon processing to combine TSV, interposers and high quality passive components Frederic Voiron, Senior R&D Engineer IPDIA | |||
| 11:15 | Advances in TSV technologies from the MEMS Perspective Thorbjörn Ebefors, Chief Technologist, co-founder and VP of R&D SILEX Microsystems | |||
| 11:40 | STMicroelectronics Strategy on 3D Integration Jean Michailos, 3D R&D Technology Senior Program Manager STMicroelectronics | |||
| 12:05 | Lunch Break - Exhibition Venue | |||
| 13:35 |  | KEYNOTE - From SnAg-Bump to 3D chip stacking – The European Backend and Packaging Agenda Jon Greenwood, Senior Director Package Technology Integration GLOBALFOUNDRIES | ||
| INSPECTION AND METROLOGY Chairman: Margarete Zoberbier, Business Development Manager 3D, Suss Microtec | ||||
| 14:00 | Inspection and Metrology Solutions for TSV High-Volume Manufacturing Rajiv Roy, VP Business Development and Director of Back-End Product Management Rudolph Technologies | |||
| 14:25 | Versatile Optical System for Metrology & Inspection of 3DIC TSV Integration Process Gilles Fresquet, Head of Semiconductor Business Unit Fogale Nanotech | |||
| 14h50 | Coffee Break - Exhibition venue | |||
| TESTABILITY Chairman: David Butler, VP Marketing, SPTS | ||||
| 15:20 | Practical Design-for-Test for 2.5D- and 3D-Stacked ICs Erik Jan Marinissen, Principal Scientist imec | |||
| 15:45 | 3D and 2.5D Test Challenges – Getting to Known Good Die & Known Good Stack Gary Fleeman, Senior Director Business Development Advantest | |||
| 16:10 | 3D Technology Fusion – Is KGD Good Enough? | |||
| 16:35 | Closing remarks Francoise von Trapp, Editorial Director 3D InCites | |||
| 16:45 | End | |||
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In addition to the conferences, European 3D TSV Summit will feature:
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| Register now ! | ||||
| (*) Access to clean room visit is pending CEA security authorities approval | ||||
