European 3D Summit – Heterogeneous Integration driving 3D   ●   22-24 Jan 2018   ●   Dresden, Germany

Abstracts and Biographies 


Heterogeneous Integration: A Driving Force and Enabling Technology for 3D SiP Products

W. R. Bottoms Ph.D​, Chairman, 3MTS

The adoption of 3D integration for high volume products has been slow to develop even with the technology available. The early adopters have been shipping specialized low-volume products for several years but complex 3D-TSV SiP architecture was not adopted for high volume products. Today we see difficult challenges to future growth presented by power requirements, performance requirements, size, latency, thermal density, reliability, bandwidth density and cost. Now that we are facing the economic end of Moore’s Law Scaling for many products, driving forces for adoption have changed and new architectures, new materials and new processes will be required. Heterogeneous Integration (HI) is an enabling technology that offers solutions to these difficult challenges.
As system level forces drive complex 3D-TSV SiP adoption, several factors such as cost and thermal density which were factors delaying adoption are now driving forces for adoption. New products with lower power per function, lower thermal load per function, smaller size and lower cost per function are here today and more are in process. These solutions all involve heterogeneous integration. Heterogeneity by circuit fabric type, device type, materials and process nodes enables the use of the best component for each function and each component can be built with the most efficient processes and the most appropriate materials for its function. HI capability has been demonstrated, the supply chain is maturing and the activity has shifted from packaging to system integration with system level design, component specification, component manufacturing and system assembly and test. The difficult challenges and the technologies enabling this transition will be discussed.
Dr.  Bottoms received a B.S. degree in Physics from Huntington College in Montgomery, Alabama in 1965, and a Ph.D in Solid State from Tulane University in New Orleans in 1969 and is currently Chairman of Third Millennium Test Solutions. He has worked as a faculty member in the department of electrical engineering at Princeton University, manager of Research and Development at Varian Associates, founding President of the Semiconductor Equipment Group of Varian Associates and general Partner of Patricof & Co. Ventures. He has served as Chairman and CEO of many companies both public and private.
Dr. Bottoms has also served in a number of Government Advisory positions including Chairman of the Board on Assessment for NIST and a member of the Technical Advisory Committee on export controls for the US Commerce Department.
Dr. Bottoms has participated in the start up and growth of many companies through his venture capital activity and through his own work as an entrepreneur. These include companies in a wide range of industries. Among these companies are:
  • Business Insurance Company
  • Chevy’s Mexican Restaurants
  • Credence Systems
  • Johnny Rockets
  • Microelectronics Packaging Inc.
  • NanoNexus
  • SBA Materials
  • Southwest NanoTechnologies
  • Tessera
  • Third Millennium Test Solutions

Dr. Bottoms currently serves as:

  • Emeritus Member of the Board of Tulane University
  • Co-Chair of the Heterogeneous Integration Roadmap
  • Chairman of the SEMI’s Awards Committee
  • Chairman of the Packaging and Package Substrates Technical Working Group for INEMI
  • Member of the Board of MIT’s Microphotonic Center
  • Chairman of Fluence Analytics
  • Chairman of Third Millennium Test Solutions


2018, the golden year for 3D integration

Thibault Buisson​, Business Unit Manager, Yole Développement

Although several new materials and processes are being developed to address the challenges of upcoming technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. The semiconductor industry is looking for technology solutions combining performance, integration and cost not limited to the CMOS scaling. In that context the Three-dimensional (3D) technology using vertical interconnect is one the emerging option, considered today the most advanced technology that could enable various heterogeneous integration. If the well-known Through Silicon Via (TSV) remains the key enabler of this innovative package, it has opened the doors to new stacking technology such as hybrid bonding. 3D technology adoption was fostered by the commercialization of products addressing several applications and markets. The presentation will illustrate how 3D brought solutions to high-end applications such as supercomputing and datacenters but also how it spread in middle end products for consumers markets such as CMOS image sensor. Besides the applications, this presentation will show how the supply chain organized and collaborated to respond to 3D integration challenges. Emerging needs such as deep learning brought out more challenges to the IC but also to the packaging industry. In the presentation we will review if emerging needs in computing and datacenters will significantly speed up or not the 3D-based devices adoption.   





High-Performance Applications:  2.5D and Alternatives

Dick James, Senior Analyst, TechSearch International, Inc.

High-performance applications have many choices to meet packaging needs.  These choices include 2.5D or silicon interposers, organic interposers including Intel’s EMIB, and new fan-out wafer level packaging (FO-WLP) on interposers.  Discussed are numerous packages types and the use of high bandwidth memory (HBM).  HBM is a 3D memory stack with through silicon vias (TSVs).  This presentation examines the drivers for each application domain and the reasons for the package format adoption. 

Dick James is a Senior Analyst with TechSearch International, Inc.  which has provided market research and technology trend analysis in the semiconductor industry since 1987.
Prior to joining TechSearch, Dick was Senior Fellow/Technology Analyst at Chipworks (now TechInsights) for over 20 years, acting as a consultant to staff and customers, dealing with the microstructural characterization of devices, both process and packaging.  He is now a Fellow Emeritus at TechInsights, and also a sought-after speaker at technical conferences and a popular blogger at TechInsights.com and Solid State Technology. 
Dick graduated in 1971 with a M.Sc. in Microelectronics and Semiconductor Devices from the University of Southampton in England, and a B.Sc. in Applied Chemistry from the University of Salford. He has over 45 years of experience in process development, design, manufacturing, packaging and reverse engineering of semiconductor devices.



Latest Trends on Heterogeneous Integration Substrate

Henry H. Utsunomiya, President, Interconnection Technologies, Inc.


The semiconductor devices have been provided increase of functionality per unit area and decrease of cost per function that drives system integration of electronics industry. In addition, Moore’s Law of semiconductor production process scaling is the backbone of system integration. However, the semiconductor device technology is heading the basic physical limits and economical limits to CMOS scaling. Heterogeneous Integration (HI) that is well known as “More than Moore” refers to the integration of separately manufactured components into a higher-level assembly that in the aggregate provides enhanced functionality and improved operating characteristics. And HI provides multiple functions associated with a system and/or subsystem by combination of multiple active components and passive components of different functionality such as analog components, LSI, MEMS, RF components, optical components, biological components, and passive components assembled in a single unit such as system-in-package (SiP) , system-in-module (SiM) and/or system-in-board (SiB).

In this presentation, I will introduce the back-ground of global packaging trends toward next generation of electronics industry led by IoT and Industrie 4.0 and solutions provided by HI including 2.5D/3D IC integration, advanced 2D integration by board level, wafer level and panel level. Especially, a glass packaging substrate is one of a promising technology for filled a gap between CMOS based semiconductor scaling and organic substrate or printed circuit board based design rule with affordable cost.

Henry Utsunomiya is a globally recognized authority in high technology with experience in compound semiconductor wafer technology marketing as well as expertise in PBGA, MCM-L and other IC packaging substrate technologies. His very active 40 year career includes more than 30 years of involvement and experience in international electronics / semiconductor standards and forecasting committee activity with such industry association as IPC, iNEMI, ITRS, JEITA, JIEP and JPCA. 
Mr. Utsunomiya is licensed by the Japanese Government (METI) as a small and medium enterprise business consultant and has continued in this activity since early 1999. He is also a member of the Jisso International Council, iNEMI, IPC and ITRS Roadmap committee and has been a key contributor to the Jisso Roadmap published by the EIAJ and JEITA since its first printing. His important contributions to the electronics industry have been recognized as he is a recipient of the IPC President’s Award.




Opportunities and Challenges in 3D Stacked Components

Bob Sankman, Director, Assembly Technology Pathfinding, Intel

The value proposition for an integrated circuit can lose its attractiveness when the diversity of device types required, or the overall chip area exceeds the economic feasibility of a fabricating a monolithic device. Multichip packaging can be a solution for these challenges, and has been used extensively in the semiconductor industry. However, certain high performance applications require interconnect densities, or interconnect lengths that cannot be realized with 2 dimensional side-by-side multi-chip packages. The industry solution for these interconnect challenges, and to help meet reduced package footprint constraints, is trending towards 3D stacked components. While resolving key yield, interconnect or form factor issues, 3D stacked devices generate new challenges with assembly process and materials, thermal dissipation, electrical parasitics, debug and test. Advantages and key challenges involved with 3D stacking components in integrated circuit packaging will be discussed.

Bob Sankman is an Intel Fellow and the director of package and assembly pathfinding in the Assembly Test Technology Development (ATTD) group at Intel Corporation. He is responsible for directing the definition of packaging and assembly activities for Intel’s advanced logic products.

Before assuming his current role, Sankman served as the pathfinding manager for the Assembly Test Technology Development group, where he was responsible for defining packaging technology to support all Intel logic processes. Earlier in his Intel career, he managed package design and core competency teams. Sankman joined Intel in 1980 as a wafer fab process engineer. Sankman has earned over 30 patents in the field of electronic packaging and has been honored with three Intel Achievement Awards. He has also contributed his expertise to numerous technical papers.  Sankman earned his bachelor of science degree in chemical engineering from the University of Illinois in 1980.



NAND: Wire Bond's Last Stronghold for 3D-Integrated Devices

Tom Gregorich, Senior Director Package Engineering, Western Digital

At this time NAND and other Non-Volatile Memory technologies are nearly 100% dependent on wire bond technology for 3D-integrated devices, and are also one of industry’s last strongholds for wire bond interconnect.  At the same time, NAND utilizes some of the most complex 3D silicon structures in the industry.  Key questions for the NAND industry are:  

  • Will wire bonds meet the NAND industry’s interconnect needs forever?
  • If not, what interconnect technologies could replace the wire bond?

In this presentation we will describe:

  • Why wire bond interconnect is such a good fit for 3D NAND
  • What is needed to extend the usage of wire bonds in future NAND products
  • Lessons-learned from the deployment of TSVs in DRAM and Logic
  • Technological requirements for next-generation NAND and other Non-Volatile Memories

Thomas Gregorich is Senior Director of Package Technology at Western Digital where he is responsible for development of all NAND products, including wire bond, flip chip and hybrid flip chip. Previously Mr. Gregorich held Vice-President and Director-level positions at Micron, Broadcom, MediaTek and Qualcomm.  At Micron Mr. Gregorich qualified the Company’s first commercial TSV product.  While at Qualcomm he established the Package Engineering department and for 12 years led the development of Qualcomm’s small form-factor package portfolio including NSP, CSP, BCC, QFN, POP and PIP.  A large portion of the Qualcomm portfolio is 3D and utilizes both wire bond as well as flip chip interconnects.  Prior to his position at Qualcomm, Mr. Gregorich worked for Motorola and had assignments in the Semiconductor Products Sector and Corporate Research, both in the United States as well as Japan, Taiwan and China.  Mr. Gregorich has a BS in Mechanical Engineering from Bradley University, an MBA from Northern Illinois University and is a Senior Member of IEEE.



Thermo-Mechanical Investigations on 3D Hybrid Stacking

Clément Sart, Modeling & Characterization Junior Engineer, STMicroelectronics

In order to pursue the trend towards further miniaturization and performance for microelectronics products, new architectures are continuously developed. A progressive shift towards 3D integration strategies is observed in the industry, requiring specific processes to manufacture the vertical interconnections between the different tiers of the stacked chips. Among them, metal-dielectric hybrid bonding (HB) is one of the most promising, thanks to its very low pitch capacity. However, it leads to specific mechanical and thermomechanical issues, in particular those related to (i) hybrid bonding quality and reliability, (ii) wire-bonding and probing on backside pads and (iii) thermomechanical stress effects on device performance, on which very few is known at the moment. Aiming to provide a better physical understanding on these topics, optimize assembly and pad structures (HB, wire-bond, probing), as well as evidence and optimize stress effects on devices, both numerical and experimental investigations are carried out, e.g. finite element modeling, in-situ mechanical sensors implementation, four-point bending experiments. In this presentation, the benefits of the metal-dielectric hybrid bonding technology will be outlined, and the main results obtained to secure product integration from a thermomechanical perspective will be discussed.

Clément Sart is currently with STMicroelectronics Crolles (France), where since 2015 he prepares a PhD thesis (University of Grenoble) on Thermo-mechanical Simulations and Experiments on 3D Stacking. He graduated from the Institut Supérieur de Mécanique of Paris as a mechanical engineer and received a master’s degree in structural dynamics and materials from Ecole Centrale Paris in 2014.



Manufacturable Low Temperature Direct Bond Technology Driving Heterogeneous Integration and High Density 3D System Applications

Paul Enquist, Vice President, 3D R&D, Tessera Xperi

The development of manufacturable low temperature direct bond technology has enabled and is expected to further enable a number of heterogeneous integration and high density 3D system applications.  This presentation will cover specification, capability and implementation of two key direct bond technology variations and applications that have driven and are expected to continue driving adoption by a number of fabless, foundry, and IDM customers.  These two variations, known as ZiBond® and DBI®, are distinguished by homogeneous insulating and >108/cm2 interconnect density hybrid bond capability, respectively.  A low temperature bond strength stronger than silicon, in-situ scalable 3D interconnect that can eliminate or simplify TSV technology and low back end of line cost of ownership have combined to make these technologies of choice for image sensor and RF applications.  The partitioning of 2D SoC designs into multi-node stacked 3D designs with significant cost savings is expected to drive further adoption.  Furthermore, a 25um bondline capability and potential state of the art hermetic performance are expected to result in widespread implementation for a variety of MEMS applications including those requiring CMOS integration.

Dr. Enquist is V.P. of 3D R&D at Tessera.  He has over 30 years of experience, over 130 publications and presentations and over 50 issued US patents related to high speed devices and circuits, low temperture direct bonding and 3D integration.  He holds Ph.D. and M.S. degrees in Electrical Engineering from Cornell University and a B.S. degree in Engineering from Columbia University.  He is an IEEE senior member, member of Tau Beta Pi and Eta Kappa Nu.



3D Packaging for Integrated Circuits - Putting Together All of the Pieces

Rainer Käsmaier​, VP Marketing at LFoundry

With the advent of the Internet of Things and the application of wafer stacking technology in high volume products such as image sensors, 3D IC assemblies are being used to deliver new products into the market place. In addition to continuing to reduce the cost of using this capability, consideration needs to be given to the challenges of how 3D IC heterogeneous integration will be used in the IOT, the tools that will be used to create these 3D IC assemblies, and establishing an integrated supply chain to build those assemblies. This presentation will review these challenges are and how they can be addressed.

Dr. Rainer Käsmaier held various management positions in the last 20 years within the semiconductor industry at Siemens, Infineon, Qimonda, and LFoundry in R&D, Engineering, Production and Sales & Marketing / Business Development.
He is currently the VP Marketing at LFoundry, a SMIC company, overseeing SMIC’s Europe marketing as well as LFoundry’s market strategy and business development. Rainer is also member of the scientific supervisory board at CiS Forschungsinstitut für Mikrosensorik Erfurt, Germany.



Advanced Panel-Level Interconnect and Embedding Technologies for 3D Module Integration

Martin Schrems, Director Strategy & Business Development, AT&S

Miniaturization in electronics and further 3D integration of functions is driven by (system) cost and form factor reduction. Performance advantages are additionally achieved e.g. due to shorter and more reliable electrical interconnects between components.  While consumer applications such as smartphones and smartwatches continue to be key drivers, there are also application opportunities in other areas such as Medical, Industrial or Automotive. The presentation will briefly review the benefits and fields of applications of the different 3D integration concepts including 3D/TSV, Fan-Out, System-in-Package (SiP), as well as System-in-Board (SiB) using embedding of components. Trade-offs between wafer- and panel-level technologies will be briefly summarized before focusing on analysing the technical and application benefits of panel-level module integration more deeply. Mastering the combination of PCB, substrate, embedding and assembly technology as well as a good understanding of semiconductor components and collaboration along the value chain is found to be of key importance.  Examples of already successfully introduced products such as DCDC converters with integrated passives, and a variety of products in the R&D- or introduction- phase such as power or sensor modules using SiB embedding technology are shown. Integration of larger numbers of active and passive components, as well as electrical shielding and the possibility to integrate heat sinks for thermal management are understood as key advantages in using such panel-/board-level 3D integration.

Dr. Martin Schrems, “Director Strategy & Business Development” joined AT&S AG in 2017. In his current position, Martin  is responsible for the overall corporate strategy, marketing, and  business development reporting to the CEO. He has 20 years’ experience in the semiconductor industry with previous positions held at ams AG (Austria),  Infineon (Germany),  Siemens Semiconductors (US), and  TOSHIBA (Japan). He holds a PhD degree in Electrical Engineering (1991) and a Master of Science in Physics (1988) both from the Technical University Vienna as well as an Executive MBA from IMADEC University (2006).



3D WLP packaging for high frequency application using embedded passives

Marcel Wieland, SR MGR Technology Development, GLOBALFOUNDRIES


GF´s new 22FDX-mmw technology is targeted to serve ultra low power, digital data processing and analog IP integration and allows system architects to design IP into one single SoCs. To package these mixed signals SoC, our industry is facing complex challenges by a high number of digital I/O, localized currents, hot spots, and highly sophisticated power and ground networks.  
By using wafer level packaging and materials (i.e. mold) improvement of the analog circuit can be shown on IP size and performance. 
In this talk, we will show how passive devices are getting carefully designed and characterized in a pre-layout phase. This includes 6HGz instructors used for LNA´s and high frequency splitter (60GHz) used for analog beam forming antenna array as well as the antenna array integration in a 3D WLP package (POP approach). Package test sided are used to build layout blocks to understand parasitic losses and generate S parameter models for later integration into full designs. 

Operations, engineering and technology management professional with advanced knowledge in getting results by working in an international environment; more than 10 Years’ experience in high-tech engineering; build up and ramp of new facilities; Technology transfer from/to ASIA. Verifiable track record in managing start-up and ramp of emerging technologies to volume. RF/MMW design and verification methodology and chip to package co-design/simulation.




Advanced SiP Packaging Technology

Seung Wook Yoon, Director, Advanced Products & Technology Marketing, STATS ChipPAC


System-in-package (SiP) technology has been evolving through the utilization of various packaging technology building blocks to serve diverse market needs, with respect to miniaturization, heterogeneous integration, and modularization, with the added benefits of lower system cost and faster time to-market. 
Rapidly evolving demands for greater system performance, increased functionality and reduced form factor are driving three key paradigm shifts in the microelectronics industry. First, product miniaturization and the modularization of functionality accelerates growth in system level integration. Second, increasing I/O densities and complex integration requirements in a smaller form factor are leading to a wide range of fan-in and fan-out wafer level packaging solutions. Third, higher package to package interconnection density requirement pushes the envelope of 3D package integration.
This presentation will introduce advanced SiP packaging technologies including thin flex substrate, thin die, integrated passive devices (IPD), and wafer level packaging, FOWLP for SiP and miniaturized modules for various applications.  It will also sentation will describe the new manufacturing module approach and the results of process characterization for products produced in the module.

Dr. Yoon is currently working as director of Advanced Products & Technology Marketing, STATS ChipPAC Pte. Ltd in Singapore.  His major interests are for Advanced Packaging and Integration Technology including eWLB/Fanout WLP, SiP and integrated 3D IC packaging.
Prior to joining STATS CHIPPAC LTD, He was deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 250 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging. Currently working as technical committee member of various international packaging technology conferences, EPTC, ESTC, iMAPS, IWLPC and SEMI.



The Expanding Reach of Interposer Technology

Steffen Kroehnert, Director of Technology, Amkor/NANIUM

Embedded packaging and Wafer-Level Fan-Out Technology with Chip-first/RDL-last assembly and an interconnect approach for low and high density active and passive interposers as well as advanced Flip Chip Technology with RDL-first/Chip-last assembly and interconnect approach are gaining importance in the semiconductor packaging market. These advanced packaging options are providing significant performance, form-factor and cost advantages compared to mainstream packaging technologies. The different assembly and interconnect approaches serve different application needs, and allow for 3D integration such as WL3D and WLPoP. This presentation will discuss Amkor Technology’s offerings in this area, including: SWIFT® (Silicon Wafer Integrated Fan-Out Technology), WLFO (Wafer-Level Fan-Out) based on eWLB (embedded Wafer-Level Ball Grid Array) and 2.5D silicon interposers, providing a complete set of advanced packaging technologies to create innovative packaging solutions to meet customer needs – today and into the future.

Steffen Kroehnert is Director, Advanced Packaging Technology, at Amkor Technology. Before NANIUM acquisition by Amkor Technology in May 2017, he worked for 20 years in different R&D and management positions at Siemens Semiconductors, Infineon Technologies, Qimonda and NANIUM in Germany and Portugal. Steffen is active member of several technical and conference committees of IEEE EPS, IMAPS, SMTA and SEMI. Since begin of 2016 he is chair of the European SEMI integrated Packaging, Assembly and Test (ESiPAT) Special Interest Group. Steffen is author and co-author of 23 patent filings and many technical papers in the field of Packaging Technology. He received his Master of Science degree in Electrical Engineering and Microsystems Technologies from the Technical University of Chemnitz, Germany, in 1997.



Solutions for thin and tiny dies with high die strength and for thinning WLCSP and eWLB wafers

Gerald Klug, General Sales Manager Europe, Disco Hi-Tech Europe


DISCO Corporation is a leading manufacturer for equipment and tools for wafer thinning and dicing. “Bringing science to comfortable living by Kiru (Dicing), Kezuru (Grinding) and Migaku (Polishing)” is DISCO’s mission. By combining these three core technologies, DISCO provides total solutions to meet the more and more demanding requirements of the Semiconductor industry in terms of manufacturing thin dies with high die-strength and several new approaches for advanced packaging.
Discrete devices and RFID dies, universally used in smartphones and mobile devices, tend to have narrow street widths (cut margins), partially covered with low-k and ultra low-k layers, in order to maximize the number of dies formed on the wafer. Furthermore, mobile and IoT consumer products incorporate an ever-increasing number of such circuit components.
With low-k and ultra low-k layers on top singulation processes become very challenging. In addition a part of these applications require the use of DAF-layers on the backside of the dies.
In order to fulfil all these requirements, DISCO proposes several solutions, also focusing on avoidance of side wall cracks and interfacial layer damages, such as Dicing before grinding, Stealth dicing, Reverse Dicing before grinding and Plasma dicing, combined with Ablation laser grooving by ns- or ps-laser technology.
WLCSP and eWLB applications face big issues in wafer thinning, because the wafers, due to consisting of resin mold and Silicon dies and having high bumps on the front side, tend to easily break when thickness becomes lower than the bump height. Nevertheless such low thickness is required due to increasing bump thickness. DISCO offers a unique technology to grind wafers with 200 µm high bumps down to 50 µm wafer thickness.
DISCO Hi-Tec Europe GmbH, having its facilities close to Munich airport, offers certified Dicing and Grinding Production Services, so that customers can utilize most of afore mentioned Disco technologies in production, even without investing into DISCO equipment.

Gerald Klug studied business engineering at the University of Siegen and graduated in 1998 as Dipl.-Wirt.-Ing., completing his thesis at BMW in Munich. He started his career as a designer of coil processing lines for nearly 3 years at a German machine manufacturing company, Heinrich Georg GmbH. At the end of 2000, he joined DISCO as a Sales Engineer for the area of Scandinavia. Meanwhile he has been 17 years at DISCO, nowadays operating as General Sales Manager for all Europe.



Addressing Manufacturing Challenges in High Density 2.5D Assembly

David Danovitch, Associated Professor, Electrical & Computer Engineering, Université de Sherbrooke


Miniaturization and performance of heterogeneously integrated ‘Systems in a Package’ (SiP) are strongly dependent upon density capability, comprising both the individual interconnection density (pitch) and the inter-chip/component density.  The advent of 2.5D integration has contributed significantly to increasing these densities by means of improved CTE matching and finer wiring combined with reduced liquid solder (Cu-piller, SLID bonding) interconnect and pre-applied underfill assembly techniques.  That said, cost reduction strategies inherent to the maturation of 2.5 integration demands a critical examination of the issues and opportunities for improving manufacturing yields and throughputs.  This presentation reports on collaborative work at the University of Sherbrooke and IBM Canada directed towards such examination.  Iinnovative approaches to traditional assembly processes, such as mass reflow joining, chip rework and capillary underfill, are proposed in order to enable these cost effective technologies for higher density packaging configurations.

David Danovitch is an Associate Professor at Université de Sherbrooke in the Computer and Electrical Engineering Department and holder of the NSERC-IBM Canada Industrial Research Chair in Smarter Microelectronics Packaging for Performance Scaling.  Previous to this appointment, David was a Senior Technical Staff Member at IBM Canada’s Bromont, Quebec location within the IBM Microelectronics Division, having worked with IBM for 32 years in various aspects of semiconductor device packaging.   His degrees are in Metallurgical Engineering from McGill University in Montreal, he holds 42 patents and has authored numerous technical publications.  As a member of IEEE’s Electronic Packaging Society (EPS), David also serves on a number of conference and transactions committees.



Through Glass Vias Enabling Next Generation RFFE for 5G  

Jay Zhang, Business Development Director Precision Glass Solutions, Corning Incorporated


Through glass via (TGV) technology leverages the excellent dielectric and surface properties of glass, as well as 3D passive structures. The resultant high Q inductors and capacitors combine to form miniaturized IPDs with low insertion loss, enabling new filter performance and module integration capability. Dr. Jay Zhang will introduce simulation and measurement results to illustrate the potential of TGV technology in select RFFE applications. 

Dr. Jay Zhang is a Business Development Director for Precision Glass Solutions at Corning Incorporated. In this role, he focuses on applications of glass for consumer devices. Specifically, he is focused on exploring the technical advantages of through glass vias (TGVs) over alternative technologies in the RF front-end and antenna space. He has been with Corning for 15 years with experience across multiple divisions including Display, Specialty Materials, as well as Science and Technology. Dr. Zhang graduated with a Ph.D. in Applied Physics from Yale University and an MBA from Cornell University.



Fluorine-Free MOCVD Copper Deposition for High Aspect Ratios TSV for 3D Integration  

Sabrina Fadloun, TBA


3D integration approaches significantly increase device performance and functionality, with “Through Silicon Via” (TSV) technology forming a lead element.
To achieve these improvements, the design has evolved.  Today, TSV interconnect feature sizes are more challenging for metallization, with 10:1 to 15:1 aspect ratios appearing in designs.  These devices with narrow, high aspect ratio vias require highly conformal thin metal depositions, sometimes with thermal budget restrictions in force (typically 200°C). 
An MOCVD TiN film was developed that offers a high coverage film with robust liner/barrier properties with an ability to at 200°C.  To complete the requirements for all 3D schemes, a new deposition method was required to obtain a continuous, conformal Cu seed layer after barrier deposition to initiate conformal filling by electroplating.  In this context, we developed an ultra-thin copper film deposited by MOCVD at 200°C, using a fluorine-free organometallic precursor to give a universal MOCVD barrier/seed solution for high aspect ratio TSV with or without temperature constraints. 
To give a full MOCVD metallization solution at low temperature provides a solution for all 3D integration schemes and overcomes the step coverage limitations of I-PVD approaches used with lower aspect ratio designs.

2006 Polytech’Lyon :  School of engineer specialized in Material and Characterizations.
2006 CEA-Léti : 3D Integration  - Via middle development
2011 SPTS Technologies : Senior Field process Engineer - PVD & MOCVD Process Development for TSV 3D Integration applications.
2016 SPTS Technologies : Senior Field process Engineer + PhD about MOCVD copper development for very high AR TSV.



Active Electrical and Optical 3D Interposer for High Speed Communications with High Aspect Ratio TSVs  

Sujay Ashok Charania, Institute for Semiconductor and Microsystems (IHM), TU Dresden

3DICs are industry-accepted path for future semiconductor development and TSVs are significant component for the 3D integration. High speed on chip communication is the fundamental requirement to incorporate future, performance driven applications like High Bandwidth Memories (HBM), High speed data processing and transmission, High density mobile imaging and Virtual Reality, etc. With various advantages like low power, better performance per area and shorter interconnect lengths, electrical connections through the TSVs are irresistible to overlook in 3D chip design. Apart from these advantages, to achieve a giant leap of performance, the application of 3D optical interconnects with virtually unlimited bandwidth, very high data transmission speed and practically no data loss or thermal overhead is the path to follow. 
3D interconnect network is developed using our >20:1 aspect ratio TSV development and nanoimprinting process. Both type of interconnects provide foundation for conventional (electrical interconnects) development and novel (optical interconnect) development. Our electrical interconnect development process includes skilful etching of high AR TSVs, barrier and seed layer development with cutting edge ALD and ECD of Cu. On the other hand the novel optical interconnect development process is composed of high AR TSV etching, oxidation (cladding formation), and SU-8 interconnect (core) fabrication along with nanoimprint to extend the optical interconnect in third dimension. The primary measurement suggests that the optical interconnects supports 80-100 times the data transmission speed of conventional electrical interconnects. The combination of the two brings the best of both worlds. 

The author's name is Sujay Charania, was born on 27th July, 1990 in Ahmedabad, India. He achieved his Master of Science in Nano Electronics in 2016 from Technical University of Dresden, Germany and since then he is working on his doctoral studies with the topic of development of ultra high speed optical interconnect on Si interposer as a research fellow in the project 'Atto3D' for communication infrastructures for networks in 3D chip stacks. His area of expertise is semiconductor technology and especially nanoimprint lithography. Earlier he has worked on a project on image processing at Indian Space Research Organisation, India.



Integrated Hardware Accelerators for Machine Learning in 3DIC Stacked Die Server Processors with GaN Integrated Voltage Regulators 

Don Draper, CEO, ProPrincipia

Internet traffic and data set sizes are outrunning computational capacity. In Machine Learning and Deep Learning, the training stage of deep neural graphs on massive data sets can run for hours or days on large arrays of server processors. Insights are then extracted in the inference stage. This is aided by hardware accelerator ASIC chips which provide faster and lower power optimized functions than achievable in the cores of the host processor. However, the large latency of the host processor-to-accelerator interconnect bus such as that defined by the CCIX protocol severely limits performance and raises power dissipation. The solution is to remove this bus by integrating the hardware accelerator chip with the host processor in a 3DIC stacked die configuration which greatly reduces latency, increases performance and substantially reduces power dissipation.  The interconnect length shortening of 3DIC is well-documented, providing reduced latency and lower power dissipation. Options for Wafer-on-Wafer (WoW) and Chip-on-Wafer (CoW) bonding are possible. In comparison, 2.5D implementations have much longer lateral interconnect in the interposer. In heterogeneous die stacking, the base die can be in an N-1 or N-2 older technology for reduced cost and higher yield. Finally, the possibility of swapping out the various base die enables hard IP re-use and more frequent product updates at much less cost than re-taping out the expensive host processor top die.  Performance can be further improved by implementing integrated voltage regulators (IVRs) with magnetic inductors in the base die to provide very short range, highly regulated power delivery to voltage domains in both die. The system board can now use simpler voltage regulator modules (VRMs) to deliver unregulated higher voltage at lower current to the processor. The IVRs in the base die deliver minimum ripple which allows lower Vmin and provide much faster load transient response and faster Dynamic Voltage Frequency Scaling (DVFS) providing up to 30% power reduction. Furthermore, Chip-on-Wafer 3DIC offers the possibility of integrating GaN driver transistors in the IVR for higher performance and reduced power dissipation. 
​In summary, 3DIC with integrated hardware accelerators and enhanced performance addresses the computational challenge in Machine Learning of ever-larger data set sizes. 

Donald A. Draper is Principal Analyst of ProPrincipia International Associates, based in Cupertino, California. He was formerly at Oracle Corporation as a Senior Principal Hardware Engineer. Previous positions included Circuit Design Manager at Advanced Micro Devices and at Rambus, Inc. He graduated from the University of British Columbia, Vancouver, British Columbia, Canada with a Bachelor of Applied Science in Engineering Physics and from Carleton University in Ottawa, Canada with a Masters in Engineering in Semiconductor Physics. 







Including MEMS​

Steven Haddleton, Director Sales and Business Development, Silex



3D Advanced Technologies For Neuromorphic Architectures ​

Hughes Metras, VP Strategic Partnerships, North America, CEA-Leti


Neuromorphic architectures are a very good candidate for the implementation of robust, energy efficient hardware accelerators that are increasingly envisioned by computing architecture designers. The presentation will aim at showing how advanced High density 3D integration technoloqies such as Cu-Cu hybrid bonding and Monolithic Integration will provide practical solutions to build new functions and new products.
We will present one or two examples of neuromorphic architectures targeting vision processing applications and show how they can benefit from vertical interconnects at very small pitch.
We will review current trends in the field of chip stacking and share our vision of future roadmaps and what challenges must be tackled in the next 3 to 5 years. Hybrid bonding is already available at wafer to wafer scale for vision sensors and opportunies for R&D may reside in chip to wafer approaches that will enable a variety of applications in large chips. Finally, to reach ultra high density interconnects, monolithic integration routes such as CoolcubeTM are of the essence and require process innovations (low temperature budget, interconnect layers) as well as new design methodologies and tools.

Hughes Metras works with CEA-LETI where he is project manager of the market acceleration program for 3D integration technologies.Until August 2017, he was responsible for Leti’s Strategic Partnerships in North America and was also a visiting staff at Caltech in the framework of the Alliance for Nanosystems VLSI. Over the past 6 years, he has been involved in setting up R&D programs with US semiconductor companies targeting innovations for the mobile and computing markets. To that extend, he has been instrumental in building strategic relationships with leading companies around technologies such as chip stacking, silicon photonics and advanced storage class memories that allowed him to build a good vision of market requirements in the sector of computing architectures. Previously, he was VP Marketing and Sales in charge of business development and strategic planning. He coordinated Leti's sales and marketing teams in the field of semiconductors (advanced CMOS and Heterogenous integration on  200/300 mm lines), imaging, photonic, medtech and telecommunications. He benefits from a technical background in Physics engineering (Ecole Centrale de Marseilles) and holds an MBA from the University of Miami (Florida).



Mix of Different Devices​

Christian Hoffmann, TBA, Epcos



Photonic packaging compatibility with high throughput manufacturing

Richard Langlois ​, IBM


Silicon photonics technology has the potential to bring disruptive advancements in packaging that will lower the cost and complexity to the components. One of the leading approaches to scability and cost-efficiency improvements is to enable existing high-throughput microelectronic assembly tools for single mode photonic packaging. This in turn requires self-alignment structures and efficient mode converters to standard single-mode fibers integrated on chip. The approaches developed for the optical interconnect to the photonic chip include the use of a mechanical compliant low-cost interface with integrated polymer waveguides, the use of available standard multi-fibers arrays, as well as the development of solder self-aligned flip chip assembly with sub-micron accuracy. The present will be a review of these photonic packaging solutions.

Richard Langlois graduated in engineering physics and got a M.Sc.A and Ph.D. in materials science from Ecole Polytechnique / University of Montreal, Canada.
After working for 3 years at National Research Council Canada, he joined IBM Canada in Bromont, Quebec, where he has spent more than 20 years working on the development of a variety of packaging related processes including surface finishing, chip joining and rework, thermal management, thermocompression bonding (2.5 D and 3D) and more recently silicon photonics packaging.



Comb & Hybrid Laser Driven WDM Silicon Photonic Interconnects for Exascale and HPC applications

Ashkan Seyedi, Research Scientist - Large-Scale Integrated Photonics, Hewlett Packard

This talk outlines the work done at Hewlett Packard Enterprise on photonic interconnects using key components such as micro-ring modulators, avalanche photodiodes, and quantum dot comb and hybrid ring lasers to power exascale and high-performance applications. A brief overview of individual device performance is followed by a system-scale analysis of power consumption, optical crosstalk, and overall fiber bandwidth that is achievable by the various proposed architectures. The most recent results on CMOS/Photonic chip flip-chip packaging will also be reviewed as a means to enable future architectures using these various photonic components.

Ashkan received an dual Bachelor’s in Electrical and Computer Engineering from the University of Missouri-Columbia and a Ph.D. from University of Southern California working on photonic crystal devices, high-speed nanowire photodetectors, efficient white LEDs and solar cells. While at Hewlett Packard Enterprise, he has been working on developing high-bandwidth, efficient optical interconnects for exascale and high performance computing applications.



3D Functional Partitioning for Scaled Systems

Dragomir Milojevic, Senior Scientist, imec


Future applications reduce power, increase performance and lower cost beyond what is feasible using feature scaling and Design-Technology Co-Optimization (DTCO). 3D technology offers a path forward to improve connectivity at system level, by shortening wires and lower parasitics and integrate heterogeneous functions and technologies at low cost. The challenge is to map system needs on architectures taking benefit of the 3D technology landscape: Wafer-to-wafer multi-layer and scaled TSVs down to 2um pitch, face-to-face wafer-to-wafer bonding with sub 1um pitch, Die-to-wafer 5um pitch stacking. In this presentation, we will report that functional tri-layer partitioning is a way forward to significantly reduce cost, improve performance and power consumption, including power delivery and thermal constraints.

Dragomir Milojevic received his Ph. D. in Electrical Engineering from Université libre de Bruxelles (ULB), Belgium. In 2004 he joined IMEC where he first worked on multi-processor and Network-on-Chip architectures for low-power multimedia systems. Today, part of the INSITE program at IMEC, he is working on design-technology co-optimization of advanced technology nodes and design methodologies and tools for technology aware design of 3D integrated circuits. Dragomir Milojevic holds the position of a professor at Faculty of Applied Sciences, ULB, where he co-founded Parallel Architectures for Real-Time Systems (PARTS) research group. He authored or co-authored more than 90 journal and conference articles, and served as technical program committee member to several conferences in the field.



Designing and Implementing the Packaging Technologies of the Future

Alexandre​ Arriordaz, Technical Marketing Manager, Mentor Graphics


Moore’s law is driving growth of innovative packaging technologies in response to system scaling demands. New packaging technologies such as fan-out wafer-level packaging (FO-WLP), or multi-substrate/multi-device packages like interposers and system-in-package (SiP) have entered the market in the last few years. Collectively known as high density advanced packaging (HDAP), many of these packages incorporate some element of multiple substrates or multiple devices (flat or stacked) to deliver solutions for system scaling that enable us to fit in more functionality, while extending battery life. However, new technology brings new challenges, both in design and verification. Ensuring 2D/3D interoperability throughout the process from planning to final sign-off and verification, connectivity planning and coordination of high-performance interfaces across substrate boundaries, electrical extraction and analysis of the completed assembly, and mask- level verification of individual substrate and completed assembly are just a few of the technical concerns that must be addressed. We examine these and other implementation challenges, and introduce some of the emerging solutions.

Alexandre Arriordaz is a Technical Marketing Manager for Calibre Design Solutions at Mentor, A Siemens Business, focusing mostly on Calibre Circuit Verification products. In parallel to this activity,
he is also a technical interface for various European projects dealing with R&D topics like 3D-IC or Silicon Photonics. Prior to joining Mentor 6 years ago, Alexandre was a full-custom
design engineer at Freescale Semiconductor, working on advanced testchip/SRAM compiler developments. He holds a Masters degree in Electronics from the University de Nice-Sophia-Antipolis (France).




Landscape of More Moore scaling towards 3D integration – IRDS view

Mustafa Badaroglu, Staff Program Manager, Qualcomm


Despite the fact that the scaling of ground rules slowed down due to electrical and patterning constraints, there are still feasible paths in getting the desired performance, power, and area gains from the avenue of classical More Moore scaling, However those solutions need to be augmented by 3D technologies. In this talk we will present the More Moore logic roadmap from the view point of International Roadmap of Devices & Systems (IRDS) while considering the application drivers such as mobile computing and connectivity.

Dr. Mustafa Badaroglu is staff program manager at Qualcomm managing the feasibility demonstration of advanced technologies through the supplier hub as well as enabling ramp-up of flagship chips in foundries. He has more than 22 years of execution and management experience accumulated on System-on-Chip (SoC) design from concept to volume production, process technology, and design-technology co-optimization. He received his Ph.D. in Electrical Engineering and holds a Master of Industrial Management, both from KU Leuven. He holds more than 50 published patents and he has (co)-authored over 100 publications in scientific journals/proceedings. He is the chair of More Moore section in International Roadmap for Devices and Systems (IRDS). He is a senior member of IEEE.



3D SoC Enablement Through Hybrid Wafer Bonding

Luke England, 3D Manager, GLOBALFOUNDRIES 


As CMOS advanced node scaling becomes more difficult and costly, the usage of 3D packaging to enable true z-axis BEOL wiring is inevitable. Through thoughtful 3D architecture and design, we gain the ability to significantly improve the performance per watt profile of an SoC when compared to a monolithic equivalent while continuing to shrink the overall die and package size. This presentation will discuss drivers and implementation of 3D SoC technology from a foundry perspective. In addition, the latest advances in GLOBALFOUNDRIES’ wafer bonding and TSV technologies to enable 3D SoC will be shared.

Luke England received both his B.S. and M.S. in Materials Science & Engineering from Iowa State University in 2002 and 2004 respectively. He began his career at Micron Technology and Fairchild Semiconductor working on a variety of advanced packaging development projects related to 3D/TSV, wafer level packaging, flipchip, etc. Since 2012, he has been with GLOBALFOUNDRIES, and is currently managing the 3D/TSV package development team in Malta, NY.



3D Integration for MEMS, CMOS and Sensors - Approaches for More than Moore Applications

Ronny Gerbach, Team Leader 3D-Packaging, X-Fab


In the past decades, the development in microelectronics was driven by the Moor’s Law down to node size in the nanometer range. This scaling works well for memories and microprocessors for digital applications but not for sensor applications interfacing the physical world. These kinds of applications play an important role and require the integration of analog functions into CMOS-based specialty technologies. These diversified technologies are known as “More than Moore.” In the last years, the demand for miniaturized CMOS and MEMS sensors with high performance has increased significantly. In addition to MEMS / CMOS processing, advanced technologies are required for 3D packaging and integration for achieving the needed sensor performance as well as packaging requirements. In the talk, we will present approaches and results of development activities at X-FAB. Main contents are the TSV integration into wafers for MEMS and sensor applications and the heterogeneous integration of additional functionalities on wafer level by micro-transfer-printing.

Dr. Ronny Gerbach (male) studied precision engineering from 1999 to 2003 at the University of Applied Sciences Jena. He worked as research scientist at the CiS Forschungsinstitut für Mikrosensorik GmbH in Erfurt from 2004 to 2005 focusing on the design of microoptical sensor modules. He joined the Fraunhofer Institute for Mechanics of Materials in 2005 working on mechanical and non-destructive characterization of MEMS devices. He received a PhD in mechanical engineering from the Ilmenau University of Technology in 2012. In 2012, he started working at project leader for microoptical system integration at JENOPTIK Optical Systems GmbH. Since 2016, he is team leader in the MEMS process development at X-FAB MEMS Foundry GmbH.



John Hunt, John Hunt, Sr. Director, Engineering Technical Promotion, ASE Group



John is Senior Director, Engineering, Technical Promotion, at ASE (US) Inc., and provides technical support for the Introduction, Engineering, Marketing, and Business Development activities for Advanced Wafer Level and Fan Out Packaging Technologies at ASE.
John has more than 45 years of experience in various areas of manufacturing, assembly and testing of electronic components and systems, with emphasis on the development of new technologies and processes.  He has a B.S. from Rutgers and an M.S. from the University of Central Florida.


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