European-3D-Summit-2018-Program

 
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European 3D & Systems Summit ● 28 - 30 Jan 2019 ● Dresden, Germany


 

2018 AGENDA

Monday 22, January 2018
 
 
 

 


 
10:00 
Welcome
10:10 
Presentations of Fraunhofer Group Microelectronic: "High-Performance Center MicroNano" and "Research Fab Microelectronics Germany"

Lab- Tour Fraunhofer IPMS 

14:00 End

art´otel Dresden
Location: Ostra-Allee 33, 01067 Dresden
16:00
 
Registration / Welcome Coffee 
16:45
 
Opening by Laith Altimime, President, SEMI Europe
  
Introduction
Dresden - Shaping the Future of Europe's semiconductor hub 
Dr. Robert Franke, Director Office of Economic Development, City of Dresden

Session 1: Market Briefing
Chair:              David Butler, VP Product Management and Marketing, SPTS


 
17:00
Heterogeneous Integration: A Driving Force and Enabling Technology for 3D SiP Products
Bill Bottoms, Chairman, 3MTS
17:25
2018, the golden year for 3D integration
Thibault Buisson, Business Unit Manager, Yole Développement
17:50
High-Performance Applications:  2.5D and Alternatives
Dick James, Senior Analyst, TechSearch
18:15
Latest Trends on Heterogeneous Integration Substrate
Henry H. Utsunomiya, President, Interconnection Technologies, Inc.
18:40
 
Networking Reception  
 
 
 
Tuesday 23, January 2018
 
 
 
08:00
 
Registration and Welcome Coffee
08:30
 
Opening
08:40
KEYNOTE
Opportunities and Challenges in 3D Stacked Components
Bob Sankman, Director, Assembly Technology Pathfinding, Intel
 

Session 2: Stacked Dies and Stacked Wafers 
Chair:              Jean Michailos, R&D Technology program manager for 3D, STMicroelectronics 


 
09:10
NAND: Wire Bond’s Last Stronghold for 3D-Integrated Devices
Tom Gregorich, Senior Director Package Engineering, Western Digital
09:35
Thermo-Mechanical Investigations on 3D Hybrid Stacking
Clément Sart, Modeling & Characterization Junior Engineer, STMicroelectronics
10:00
Manufacturable Low-Temperature Direct Bond Technology Driving
Heterogeneous Integration and High-Density 3D System Applications
Paul Enquist, Vice President, 3D R&D, Tessera Xperi
10:25
3D Packaging for Integrated Circuits - Putting Together All of the Pieces
Rainer Käsmaier, VP Marketing, LFoundry
10:50
 
Coffee Break
 

Session 3: Passive Device Integration
Chair:              Luke England, 3D/TSV Package Development Manager, GLOBALFOUNDRIES


 
11:40
Advanced Panel-Level Interconnect and Embedding Technologies for 3D Module Integration
Martin Schrems, Director Strategy & Business Development, AT&S 
12:05
 
3D WLP packaging for high-frequency application using embedded passives
Marcel Wieland, SR MGR Technology Development, GLOBALFOUNDRIES
 
12:30
Advanced SiP Packaging Technology
Seung Wook Yoon, Director, Advanced Products & Technology Marketing, STATS ChipPAC           
12:55
 
Lunch Break 
sponsored by Mentor Graphics
 

Session 4: Interposer Packages (2.5D)
Chair:              Beth Keser, Director, Package Engineering, Intel Europe


14:10
The Expanding Reach of Interposer Technology
Steffen Kroehnert, Director of Technology, Amkor
14:35
Solutions for thin and tiny dies with high die strength and for
thinning WLCSP and eWLB wafers
Gerald Klug, General Sales Manager Europe, Disco Hi-Tech Europe
15:00
Addressing Manufacturing Challenges in High-Density 2.5D Assembly
David Danovitch, Associate Professor, Electrical & Computer Engineering, Université de Sherbrooke

 

15:25

Through Glass Vias enabling next generation RFFE for 5G
Jay Zhang, Business Development Director Precision Glass Solutions, Corning Incorporated

15:50
 
Coffee Break
 

Session 5: Future of 3D Integration
Chair:              Severine Cheramy, Director of 3D Integration Development, CEA-Leti  


 
16:35
 
Fluorine-Free MOCVD Copper Deposition for High Aspect Ratios TSV
for
3D Integration    
Sabrina Fadloun, Senior Field Process Engineer / PhD Student, SPTS Technologies
17:00

Active Electrical and Optical 3D Interposer for High-Speed Communications with High Aspect Ratio TSVs 
Sujay Ashok Charania, Institute for Semiconductor and Microsystems (IHM), TU Dresden 

17:25
Integrated Hardware Accelerators for Machine Learning in 3DIC Stacked Die Server Processors with GaN Integrated Voltage Regulators
Don Draper, CEO, ProPrincipia
17:50 

3D Advanced Technologies For Neuromorphic Architectures
Hughes Metras, VP Strategic Partnerships North America, CEA-Leti

18:15 
End
18:30 
Shuttle Bus
18:45
 
Gala Dinner 
sponsored by JSR Micro
at Ballhaus Watzke, Kötzschenbroder Str. 1, 01139 Dresden
www.watzke.de
 
 
   
Wednesday 24, January 2018
   
08:00
 
Welcome Coffee
 

Session 6: Heterogeneous Integration & Thermal Management
Chair:             Thomas Uhrmann, Head of Business Development, EV Group


08:55
3D System Integration – Requirements and Potential Solutions
M. Juergen Wolf, Fraunhofer
09:20
Photonic packaging compatibility with high throughput manufacturing
09:45
Comb & Hybrid Laser-Driven WDM Silicon Photonic Interconnects for Exascale and HPC applications
Ashkan Seyedi, Research Scientist - Large-Scale Integrated Photonics, Hewlett Packard
10:10
3D Functional Partitioning for Scaled Systems
Dragomir Milojevic, Senior Scientist, imec
10:35
 
Coffee Break
 

Session 7: Systems & Applications of 3D-Integration Technology
Chair:              Hugo Pristauz, Vice President, BESI


11:10
Designing and Implementing the Packaging Technologies of the Future
Alexandre Arriordaz, Technical Marketing ManagerMentor Graphics
11:35
Landscape of More Moore scaling towards 3D integration – IRDS view
Mustafa Badaroglu, Staff Program Manager, Qualcomm
12:00
3D SoC Enablement Through Hybrid Wafer Bonding
Luke England, 3D Manager, GLOBALFOUNDRIES 
12:25
3D Integration for MEMS, CMOS and Sensors - approaches for More than Moore Applications
Ronny Gerbach, Team Leader 3D-Packaging, X-FAB
12:50
Fan Out – Transformation from WLCSP to 3D  
John Hunt, Sr. Director, Engineering Technical Promotion, ASE Group
13:15
 
Closing Remarks
13:20
 
Lunch Break
   

List of the Steering Committee

Eric Beyne

IMEC

David Butler

SPTS Technologies

Severine Cheramy

CEA-Leti

Luke England

GLOBALFOUNDRIES

Andreas Erhart

Evatec

Beth Keser

Intel Europe

Stefan Lutter

SUSS MicroTec

Jean Michailos

STMicroelectronics

Hugo Pristauz

BESI

James Quinn

Scint-X

Franz Schrank

ams AG

Thomas Uhrmann

EV Group

M. Juergen Wolf

Fraunhofer IZM

 

 


Contact

For further details, please contact:

Christina Fritsch
Sr Manager Conferences 
and Programs, 
cfritsch@semi.org