TestVision 2020 - Program

Test Vision 2020 -  2018 Program

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2018 Call for Papers & Posters

To present at the workshop, authors are invited to submit an abstract at http://www.semiconwest.org/call-papers
Each submission should include: title, full name and affiliation of all authors, abstract (up to 500 words), and keywords.  Identify a contact author and include a number phone and e-mail address. Authors looking to submit full papers or draft presentations may do so through the SEMICON West Call for Papers link above.

Submission deadline extended! Submissions must be received no later than May 4, 2018.  Authors will be notified of the disposition of their presentation by May 25, 2018 and must submit the final presentation by June 22, 2018 for inclusion in the Workshop Notes, which will be provided to the attendees for download prior to the start of the workshop.  Optionally, an extended abstract or full paper can be included in the notes.


2017 Program

Survey Links

Download available PDF presentations (password protected, provided to registered attendees):

  • Day 1 (download alternate .zip file format here)
  • Day 2 (download alternate .zip file format here)

   Test Vision Program - Wednesday, July 12, 2017   




8:00 AM - 8:30 AM  On Site Registration
8:30 AM - 10:00 AM Welcome Session & Keynote
8:30 AM - 8:35 AM Welcome Remarks – General Chair: Rick Marshall, ACT Environmental Services
8:35 AM - 8:45 AM Program Review - Program Chair: Paul Berndt, NW Test Engineering, LLC
8:45 AM - 10:00 AM​ KEYNOTE : “Myth vs. Reality; Urban Legends of Semiconductor Test
Greg Smith – President, Teradyne Semiconductor Test Division

Keynote Abstract: When the semiconductor industry is viewed over long time scale, there is a clear pattern of new technologies and markets disrupting the status quo.  In each of these disruptions there are winners and losers.  The problem that we face as suppliers in this industry is telling the difference between innovations that will remake the industry, like CMOS technology, Personal Computers, and mobile communications, and ones that don’t like NMT DRAM, bubble memory and Gallium Arsenide.  Similarly, IC test has been transformed over time by DFT, multisite test and chip scale packaging, but other trends have not panned out.  This talk will look at some of the nascent trends and technologies in the semiconductor end market like ADAS and IoT.  It will also examine trends in IC manufacturing like 3D-IC, contactless test and System Level Test.  The objective is to sort the ones that will be truly transformative over the next 10 years from the ones that end up fading into nothing but urban myths.

Keynote biography: Mr. Smith joined Teradyne in 2006 as a semiconductor test product manager.  He has served in a variety of roles at Teradyne including Manager of the Complex SOC Business Unit, and Vice President of SOC Marketing in the Semiconductor Test Division.  Mr. Smith has over 30 years of engineering, management and marketing experience in semiconductor test.  Mr. Smith earned a Bachelor’s degree in Electrical Engineering from the University of Pennsylvania.  
10:00 AM - 10:15 AM Break
10:15 AM - 11:30 AM Session 1: Best ATE Paper + What to do with Test Data? (Session Chair: Ben Brown, Xcerra)
10:15 AM - 10:40 AM 1.1  2016 Best Paper Award and Presentation - Ben Brown, Xcerra, will announce the Best Paper
10:40 AM - 11:05 AM 1.2  Adaptive Test HIR Team Update - Mark Roos, Roos Instruments
11:05 AM - 11:30 AM 1.3  "Supplier Quality Network" - Dan Sebban, Optimal+
11:30 AM - 1:00 PM Lunch Break and Poster Session
  Poster 1:     eMapping: Bridging the Gap between Wafer Sort and Final Test without ECIDs - Michael Pas / Joseph A. Boduch, Texas Instruments
  Poster 2:     Production-Friendly SRAM Memory Bitmapping Flow - Sean O’Mullan, AMD
  Poster 3:     Multi-Variate Part Average Testing - A Case Study - Wes Smith, Mentor / Jochen Stephan, Micronas
  Poster 4:     Dynamic Rds(on) Testing - Peter Hancock / Gordon Leak, Focused Test, Inc.
  Poster 5:     Burning the Carpets: Multiplexing to Improve Efficiency - Jim Farrell, Celerint
  Poster 6:     Multiplexing on Steroids - Harry Roberts, Celerint
1:00 PM - 2:15 PM Session 2: Test Quality Challenges (Session Chair: Stacy Ajouri, Texas Instruments)
1:00 PM - 1:25 PM 2.1  “Continuous Deployment for Production Test” - Matt Lilie / Jonathan Boyce, AMD
1:25 PM - 1:50 PM 2.2  “Contact Resistance Challenges and a Solution” - Dave Armstrong, Advantest​​
1:50 PM - 2:15 PM 2.3  “Accelerating Time to Market with SW, HW, and Data Reuse Across the Design Cycle” - Travis White, National Instruments
2:15 PM - 2:30 PM Session Raffle then BREAK
2:30 PM - 3:45 PM Invited Speaker
  “5G Heterogeneous Networks and Implications on RF IC Test”
Dr. Jeorge S. Hurtarte – RF Market Segment Manager at Teradyne Inc.

Abstract: 5G in its widest definition promises the convergence of local and wide area networks for seamless reliable, low latency and high-throughput connectivity. Heterogeneous networks will include 4G, 4G LTE, and 5G macro cells in the low frequency bands; 5G small cells and Wi-Fi in both the low frequency and mmWave bands, as well as fiber and device-to-device communications. This paper provides an overview of the 5G heterogeneous network components, their characteristics, and the resulting use cases possible, and the implications on RF IC test. From an RF IC test perspective, it means that band-specific modular instrument architectures will be required to address a variety of frequency bands and higher bandwidths; advanced contacted signal delivery techniques for wafer probe and package test will be required; and even possibly radiated signal delivery techniques for handler package test may be needed.

Biography: Dr. Jeorge S. Hurtarte is currently RF Market Segment Manager at Teradyne Inc., Boston, Mass. Prior to joining Teradyne, Dr. Hurtarte held various executive positions at TranSwitch and Rockwell Semiconductors. Dr. Hurtarte holds Ph.D and BS degrees in electrical engineering, a MS in Telecommunications, and a MBA. Dr. Hurtarte has been in the Advisory Board of Directors of the Global Semiconductor Alliance, TUV Rheinland of North America, and NSF's Wireless Internet Center for Advanced RF Technology. Dr. Hurtarte is a voting member of the IEEE 802.11 working group and secretary of the 802.11ay task group. He is also the lead co-author of the book Understanding Fabless IC Technology and is currently working on his second book on the convergence of 5G local and wide area networks.
3:45 PM - 5:00 PM Reception and Poster Session Continued

   Test Vision Program - Thursday, July 13, 2017   




8:00 AM - 8:30 AM On-Site Registration
8:30 AM - 9:45 AM Session 3: Next Gen RF Test Challenges (Session Chair: Derek Floyd, Advantest)
8:30 AM - 8:55 AM 3.1  “5G An Evolutionary Revolution on Test” - John Shelley, Xcerra
8:55 AM - 9:20 AM  3.2  “80+ GHz Low-Loss Transmission from Tester to DUT” - Sandeep Sankararaman, Don Thompson and Shakeel Siddiqui, R&D Altanova
9:20 AM - 9:45 AM 3.3  “5G Lessons Learned from Auto Radar Testing” - Roger McAleenan, Advantest
9:45 AM - 10:10 AM 3.4  "Production Level On-Wafer Probe of Multi-Channel 77 GHz Radar Transceiver Chipset" - Jeff Finder / Jory Twitchell, NXP Semiconductor
          Presentation sponsored by:
10:10 AM - 10:30 AM Thursday Morning Raffle then Break
10:30 AM - 12:00 PM PANEL: When Mega Wireless Trends Become Reality for Test
  The near future looks very different, as technologies like 5G and automotive radar are changing the rules for IC and device level test.  Many of these devices are characterized by carrier frequencies in the tens of GHz, multiple GHz of real-time bandwidth, and system-level embedded software making critical decisions. We see this in 5G cellular, with heavy attention on the 28 GHz, 40 GHz, and 73 GHz bands combined with the impeding reality of massive MIMO technology.  The rules for wireless design and test have changed and 6 GHz is starting to feel more like DC.  What is the impact on ATE and production test requirements.
  Panelists will include:
  • Mark Roos, Roos Instruments
  • John Shelley, Xcerra
  • Adam Smith, Teradyne-LitePoint
  • Charles Schroeder, National Instruments
  • Adrian Kwan, Advantest
12:00 PM - 1:00 PM Lunch Break
1:00 PM - 2:15 PM Hot Topic - Audience Poll (Moderator: Paul Berndt, NW Test Engineering LLC)
  "System Level Test, a.k.a. SLT,
     - Questions for the Test Community to Answer"

System Level Test, SLT, is becoming a hot topic.
In this session, we would like to put forth some questions to the audience to answer with respect to SLT, and see what the Test community sees as the issues and challenges going forward.
We will raise the questions one by one providing some time for the audience to answer in an online poll and then show the results real-time.

  • Paul Berndt, NW Test Engineering LLC
  • Anil Bhalla, Astronics Test Systems
  • Harry Chen, MediaTek, Inc.
2:15 PM - 2:25 PM Thursday Afternoon Raffle
2:25 PM - 3:15 PM SESSION 4:  System Level Test Challenges (Session Chair: Luke Schreier, National Instruments)
2:25 PM - 2:50 PM 4.1  "The Challenges of Testing IoT Modules for Mass Production” - Kotaro Hasegawa, Advantest
2:50 PM - 3:15 PM 4.2  "No Escape: Key Trends Driving Need for More System-Level Test" - Anil Bhalla, Astronics
3:15 PM - 3:30 PM CLOSING REMARKS & Workshop Raffle
  Closing Remarks - General Chair: Rick Marshall, ACT Environmental Services